SLASEC8B February 2017 – January 2019 PGA460-Q1
The PGA460-Q1 device uses multiple internal regulators as supplies for the internal circuits. The analog voltage regulator (AVDD) requires an external capacitor of 100 nF. The power-supply block generates precision voltage references, current bias, and an internal clock. An additional regulator (IOREG) generates the supply voltage for the USART pins (RXD, TXD, and SCLK), DECPL pin, and TEST pin for their digital functionality. The AVDD and IOREG regulators are not intended to support any external load. The external capacitors are recommended to be placed as close as possible to the related pins (AVDD and IOREG). The PGA460-Q1 device starts to power up when a voltage is applied to the VPWR pin. The internal power-on reset (POR) is released when all regulator supplies are in regulation and the internal clock is running. During low-power mode, the IOREG regulator is powered up while the other regulators shut down to conserve power.