SLASEC8B February 2017 – January 2019 PGA460-Q1
The PGA460-Q1 device includes a USART digital communication interface. The main function of the USART is to enable writes to and reads from all addresses available for USART access. This function include access to most EEPROM-register and RAM-register memory locations on the PGA460-Q1 device. The USART asynchronous-mode (UART) digital communication is a master-slave communication link in which the PGA460-Q1 is a slave device only. The master device controls when the data transmission begins and ends. The slave device does not transmit data back to the master device until it is commanded to do so by the master device. A logic 1 value on the UART interface is defined as a recessive value (weak pullup on the RXD pin). A logic 0 value on the UART interface is defined as a dominant value (strong pulldown on the RXD pin).
The UART asynchronous-mode interface in PGA460-Q1 is designed for data-rates from 2400-bps to 115200-bps operation, where the data rate is automatically detected based on the sync field produced by the master controller. Other parameters related to the operation of the UART interface include:
Figure 20 shows the bit timing for USART asynchronous mode. Both data and control are in little endian format. Data is transmitted through the UART interface in byte-sized packets. The first bit of the packet field is the start bit (dominant). The next 8 bits of the field are data bits to be processed by the UART receiver. The final bit in the field is the stop bit (recessive). The combined byte of information, and the start and stop bits make up an UART field. Figure 21 shows the standard field structure for a UART interface field.
A group of fields makes up a transmission frame. A transmission frame is composed of the fields required to complete one transmission operation on the UART interface. Figure 22 shows the structure of a data transmission operation in a transmission frame.
Each transmission frame must have a synchronization field and command field followed by a number of data fields. The sync field and command fields are always transmitted by the master device. The data fields can be transmitted either by the master or the slave depending on the command given in the command field. The command field determines the direction of travel of the data fields (master-to-slave or slave-to-master). The number of data fields transmitted is also determined by the command in the command field. The interfield wait time is 1-bit long and is required for the slave or the master to process data that has been received, or when data must change direction after the command field is sent and the slave device must transmit data back to the master device. Time must be allowed for the master and slave signal drivers to change direction. If the UART interface remains idle in either the logic 0 or logic 1 state for more than 15 ms, then the PGA460-Q1 communication resets and expects to receive a sync field as the next data transmission from the master device.