SLASEC8B February 2017 – January 2019 PGA460-Q1
For fast (8 Mbps) communication between the master MCU and the PGA460-Q1 device, a fast USART synchronous mode is implemented. This mode uses and is only available on the RXD and TXD pins and is also using the SCLK pin as a clock input for communication to the device. In this mode the USART interface acts as a serial-shift register with data set on the rising edge of the clock and sampled on the falling edge of the clock. Differently than the USART asynchronous mode, the synchronous mode communication frame does not include a start, stop, nor interfield wait bit which means that as soon as the data in one frame has completed, the next communication data frame follows immediately. USART Synchronous Mode is identical to a Serial Peripheral Interface (SPI) without a chip-select because the addressing is handled by the three-bit UART_ADDR value to enable up to eight devices on a single bus. Figure 30 shows the bit timing in synchronous mode and Figure 31 shows the data flow for USART synchronous mode.
As shown in Figure 31, each data frame is 8-bits long with little endian format (least significant bit [LSB] first). All other functionality of the USART synchronous mode aligns with the USART asynchronous mode. Muxing of the IO pin of the USART synchronous mode is not possible and the IO pin transceiver is disabled when the device is communicating through USART in the case when the IO_IF_SEL bit is set to 1.
The PGA460-Q1 device can communicate in USART synchronous mode immediately when a rising clock on the SCLK pin is detected. No activation or deactivation of this mode is available.
If this communication mode is not used, the SCLK pin should be connected to GND to prevent noise triggering the clock input.