SBOS600D May   2014  – July 2018 REF2025 , REF2030 , REF2033 , REF2041

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Application Example
      2.      VREF and VBIAS vs Temperature
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1 Solder Heat Shift
    2. 8.2 Thermal Hysteresis
    3. 8.3 Noise Performance
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 VREF and VBIAS Tracking
      2. 9.3.2 Low Temperature Drift
      3. 9.3.3 Load Current
    4. 9.4 Device Functional Modes
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Low-Side, Current-Sensing Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Shunt Resistor
          2. 10.2.1.2.2 Differential Amplifier
          3. 10.2.1.2.3 Voltage Reference
          4. 10.2.1.2.4 Results
        3. 10.2.1.3 Application Curves
  11. 11Power-Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Related Links
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout Guidelines

Figure 58 shows an example of a PCB layout for a data acquisition system using the REF2030. Some key considerations are:

  • Connect low-ESR, 0.1-μF ceramic bypass capacitors at VIN, VREF, and VBIAS of the REF2030.
  • Decouple other active devices in the system per the device specifications.
  • Using a solid ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup.
  • Place the external components as close to the device as possible. This configuration prevents parasitic errors (such as the Seebeck effect) from occurring.
  • Minimize trace length between the reference and bias connections to the INA and ADC to reduce noise pickup.
  • Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if possible, and only make perpendicular crossings when absolutely necessary.