SLLSEP9H September   2015  – July 2019 SN6505A , SN6505B

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics, SN6505A
    8. 6.8 Typical Characteristics, SN6505B
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Push-Pull Converter
      2. 8.3.2 Core Magnetization
    4. 8.4 Device Functional Modes
      1. 8.4.1 Start-Up Mode
        1. 8.4.1.1 Soft-Start
      2. 8.4.2 Operating Mode
      3. 8.4.3 Shutdown-Mode
      4. 8.4.4 Spread Spectrum Clocking
      5. 8.4.5 External Clock Mode
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Drive Capability
        2. 9.2.2.2 LDO Selection
        3. 9.2.2.3 Diode Selection
        4. 9.2.2.4 Capacitor Selection
        5. 9.2.2.5 Transformer Selection
          1. 9.2.2.5.1 V-t Product Calculation
          2. 9.2.2.5.2 Turns Ratio Estimate
          3. 9.2.2.5.3 Recommended Transformers
      3. 9.2.3 Application Curves
      4. 9.2.4 System Examples
        1. 9.2.4.1 Higher Output Voltage Designs
        2. 9.2.4.2 Application Circuits
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Community Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

over full-range of recommended operating conditions, unless otherwise noted. All typical values are at TA = 25°C, VCC = 5 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOLTAGE SUPPLY
I(Vcc) Supply Current (2.8 V < VCC < 5.5) (SN6505A) RL = 50 Ω 1 1.4 mA
Supply Current (2.8 V < VCC < 5.5) (SN6505B) RL = 50 Ω 1.56 2.3 mA
IIH Leakage Current on EN and CLK pin EN / CLK = VCC 10 20 µA
IDIS VCC current for EN = 0 0.1 µA
ILKG(D1)
ILKG(D2)
Leakage Current on D1,D2 for EN=0 Voltage of D1,D2 = VCC 0.1 µA
VCC+ (UVLO) Positive-going UVLO threshold 2.25 V
VCC- (UVLO) Negative-going UVLO threshold 1.7 V
VHYS (UVLO1) UVLO threshold hysteresis 0.3 V
VIN(ON) EN, CLK pin logic high threshold 0.7 VCC
VIN(OFF) EN, CLK pin logic low threshold 0.3 VCC
VIN(HYS) EN, CLK pin threshold hysteresis 0.2 VCC
CLK
FSW D1, D2 average switching Frequency (SN6505A) RL = 50 Ω to VCC; Refer to Figure 36 138 160 203 Khz
D1, D2 average switching Frequency (SN6505B) RL = 50 Ω to VCC; Refer to Figure 36. 363 424 517 kHz
F(EXT) External clock frequency on CLK pin (SN6505A) 100 600 kHz
External clock frequency on CLK pin (SN6505B) 100 1600 kHz
OUTPUT STAGE
DMM Average ON time mismatch between D1 and D2 RL = 50 Ω 0%
R(ON) Output switch on resistance VCC = 4.5 V, ID1,ID2 = 1 A 0.16 0.25 Ω
VCC = 2.8 V, ID1,ID2 = 1 A 0.19 0.31 Ω
VCC = 2.25 V, ID1,ID2 = 0.5 A 0.21 0.45 Ω
V(SLEW) Voltage slew rates on D1 and D2 for SN6505A RL = 50 Ω to VCC; Refer to Figure 36 48 V/µs
I(SLEW) Current slew rates at D1 and D2 for SN6505A RL = 5 Ω through transformer;
Refer to Figure 37
11 A/µs
V(SLEWHF) Voltage slew rates on D1 and D2 for SN6505B RL = 50 Ω to VCC; Refer to Figure 36 152 V/µs
I(SLEWHF) Current slew rates at D1 and D2 for SN6505B RL = 5 Ω through transformer;
Refer to Figure 37
41 A/µs
ILIM Current clamp limit (2.8 V < VCC < 5.5V ) 1.42 1.75 2.15 A
Current clamp limit (2.25 V < VCC < 2.8 V) 0.65 1.85 A
THERMAL SHUT DOWN
TSD+ TSD turn on temperature 154 168 181 °C
TSD- TSD turn off temperature 135 150 166 °C
TSD- TSD hysteresis 13 17 °C