SLLSFM0A March   2022  – June 2022

PRODUCTION DATA

1. Features
2. Applications
3. Description
4. Revision History
5. Pin Configuration and Functions
6. Specifications
7. Parameter Measurement Information
8. Detailed Description
1. 8.1 Overview
2. 8.2 Functional Block Diagram
3. 8.3 Feature Description
4. 8.4 Device Functional Modes
9. Application and Implementation
1. 9.1 Application Information
2. 9.2 Typical Application
1. 9.2.1 Design Requirements
2. 9.2.2 Detailed Design Procedure
3. 9.2.3 Application Curves
4. 9.2.4 System Examples
3. 9.3 Power Supply Recommendations
4. 9.4 Layout
10. 10Device and Documentation Support
11. 11Mechanical, Packaging, and Orderable Information

• DGQ|10
• DGQ|10

### 8.3.3 Duty Cycle Control

The SN6507 implements a duty cycle control feature to provide line regulation to a certain degree through a resistor on DC pin. By making the DC pin voltage a function of the input, the duty cycle will adjust with VIN, so that VOUT can be kept constant. Compared to fixed duty cycle transformer drivers, this dynamic duty cycle control feature reduces LDO power loss for wide VIN variations by pseudo-regulating the output. For applications where input variation is within a certain range, this feature can eliminate the post-regulation LDO. Another benefit of duty cycle control is to reduce the transformer cost and size because of the limited input range to primary side of the transformer.

Figure 8-3 Schematic with duty cycle control

The calculation of DC pin resistor is shown in Equation 1, where both RDC and RCLK are in kΩ.

Equation 1. ${R}_{DC}=0.816×D×VCC×\left({R}_{CLK}+1\right)-1$

For fixed oscillator cases where RCLK is shorted to GND, a value of RCLK = 9.6kΩ should be used in the equation above to calculate RDC.

The duty cycle control can compensate for input variation up to ±35%, where line regulation within ±5% can be achieved. To achieve this range, it is recommended that duty cycle at nominal VIN is centered at 25% (D = 0.25). The transformer turns ratio needs take this duty cycle into calculation to ensure the expected output voltage level at all VIN voltages, as discussed in Section 9.2.2.5.

The duty cycle control features supports up to a certain duty cycle and VIN range. The minimum duty cycle is determined by the charge and discharge time of the gate capacitance of Power FETs, while the maximum duty cycle is limtied by the dead time (70 ns typical). For example, at 1 MHz, the adjustable duty cycle is between 10% and 43%. Exceeding above duty cycle range, the line regulation may saturate and input compensation does not work anymore. Meanwhile, if the duty cycle is lower than the minimum spec, the part may hit current limit at heavy loads. The VIN range that duty cycle feature is applicable is from 6 V to 36 V.

To enable the duty cycle control feature, an inductor is required on the output side. The selection of the output inductor should make sure the inductor current will not go into discountinous conduction mode (DCM), meaning the inductor current ramp should not drop to zero at any time. The minimum inductance LMIN is therefore calculated by the conditions that the part stays in continuous conduction mode (CCM) where the load DC current is smaller than half the current ramp amplitude seen on the inductor. Therefore LMIN is a function of the load current and switching frequency as shown by below equation where Iload is in A, fSW is in Hz, D is the duty cycle as a decimal (for 25% duty cycle, 0.25 would be used), and Lmin is in H.

Equation 2.
Figure 8-4 Waveforms in Continuous Conduction Mode (CCM)
Figure 8-5 Waveforms in Discontinuous conduction Mode (DCM)