SLLSEO9C March   2016  – August 2019 SN65DPHY440SS , SN75DPHY440SS

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Typical Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics, Power Supply
    6. 6.6 Electrical Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 HS Receive Equalization
      2. 7.3.2 HS TX Edge Rate Control
      3. 7.3.3 TX Voltage Swing and Pre-Emphasis Control
      4. 7.3.4 Dynamic De-skew
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 LP Mode
      3. 7.4.3 ULPS Mode
      4. 7.4.4 HS Mode
    5. 7.5 Register Maps
      1. 7.5.1  BIT Access Tag Conventions
      2. 7.5.2  Standard CSR Registers (address = 0x000 - 0x07)
        1. Table 6. Standard CSR Registers (0x000 - 0x07)
      3. 7.5.3  Standard CSR Register (address = 0x08)
        1. Table 7. Standard CSR Register (0x08)
      4. 7.5.4  Standard CSR Register (address = 0x09)
        1. Table 8. Standard CSR Register (0x09)
      5. 7.5.5  Standard CSR Register (address = 0x0A)
        1. Table 9. Standard CSR Register (0x0A)
      6. 7.5.6  Standard CSR Register (address = 0x0B)
        1. Table 10. Standard CSR Register (0x0B)
      7. 7.5.7  Standard CSR Register (address = 0x0D)
        1. Table 11. Standard CSR Register (0x0D)
      8. 7.5.8  Standard CSR Register (address = 0x0E)
        1. Table 12. Standard CSR Register (0x0E)
      9. 7.5.9  Standard CSR Register (address = 0x10) [reset = 0xFF]
        1. Table 13. Standard CSR Register (0x10)
      10. 7.5.10 Standard CSR Register (address = 0x11) [reset = 0xFF]
        1. Table 14. Standard CSR Register (0x11)
  8. 8 Application and Implementation
    1. 8.1 Application Information,
    2. 8.2 Typical Application, CSI-2 Implementations
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Reset Implementation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2 Detailed Design Procedure

The typical example describes how to configure the VSADJ, PRE, EQ and ERC configuration pins of the DPHY440 device based on the board trace length between the Source (Camera) and DPHY440 and the DPHY440 and Sink (APU). Actual configuration settings might differ due to additional factors such as board layout, and connectors used in the signal path.

Though the data rate in this example is 1 Gbps, device is placed near to the Sink, with a short output trace of 1 inch. Consequently, the ERC pin can be configured to have a rise/fall time of 250 ps for the edge. Further, due to the short output trace, the PRE pin must be configured to a setting of 0 dB and the VSADJ to be 200 mV. The Application Curve in Figure 22 shows the FR-4 loss characteristics of a 10 mil wide, 12 inch long trace. From this plot, the input signal trace suffers a loss of 1.5 dB at 500 MHz. Thus, the EQ setting can be either 0 dB or 2.5 dB. All the configuration settings and their corresponding inputs are tabulated in Table 16.

Table 16. Configuration Pin Settings

PIN SETTING INPUT VALUE
VSADJ 200 mV VIM
PRE 0 dB VIM
EQ 0 dB or 2.5 dB VIL or VIM
ERC 250 ps VIH

The configuration pins each have internal pull-up and pull-down resistors of 100 kΩ each. Thus, the recommendation is an external pull-up/pull-down resistors of about 10 kΩ each, to meet the requirement of the threshold levels for the VIL and VIH listed in the Electrical Characteristics table. The external resistors shown in Figure 18 should be populated to produce corresponding configuration settings, according to the list given in Table 17.

Table 17. Resistor Parameters

RESISTOR NAME VALUE
R1 Leave unpopulated
R2 Leave unpopulated
R3 Leave unpopulated
R4 Leave unpopulated
R5 Leave unpopulated
R6 10 kΩ (EQ = 0 dB) or
Leave unpopulated (EQ = 2.5 dB)
R7 10 kΩ
R8 Leave unpopulated