SLLSEO9C March 2016 – August 2019 SN65DPHY440SS , SN75DPHY440SS
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LPTXDA_ERC | LPTXDB_ERC | Reserved | HSC_ERC | ||||
RW | RW | RW | RW | R | R | RW | RW |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:6 | LPTXDA_ERC | RW | 0 | This field controls the edge rate of the DA0P/N LP transmitters.
00 – 18 ns at 70 pF (Default) 01 – 21 ns at 70 pF 10 – 15 ns at 70 pF 11 – 27 ns at 70 pF |
5:4 | LPTXDB_ERC | RW | 0 | This field controls the edge rate of the DB[3:0]P/N LP transmitters. The value in this field will be updated by hardware based on the state of the CFG[1:0] pin. Refer to Table 3 for settings based on sampled state of CFG[1:0] Software can change the value of this field at a later time.
00 – 18 ns at 70 pF 01 – 21 ns at 70 pF 10 – 15 ns at 70 pF 11 – 27 ns at 70 pF |
3:2 | Reserved | R | Reserved | |
1:0 | HSC_ERC | RW | 0 | This field controls the edge rate of the DBCP/N high speed transmitter. The value of this field will match the sampled state of the ERC pin. Software can change the value of this field at a later time.
00 – 200 ps at 1 Gbps. (ERC pin = VIL) 01 – 150 ps at 1 Gbps. (ERC pin = VIM) 10 – 250 ps at 1 Gbps. (ERC pin = VIH) 11 – 300 ps at 1 Gbps |