SLLSEO9C March   2016  – August 2019 SN65DPHY440SS , SN75DPHY440SS

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Typical Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics, Power Supply
    6. 6.6 Electrical Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 HS Receive Equalization
      2. 7.3.2 HS TX Edge Rate Control
      3. 7.3.3 TX Voltage Swing and Pre-Emphasis Control
      4. 7.3.4 Dynamic De-skew
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 LP Mode
      3. 7.4.3 ULPS Mode
      4. 7.4.4 HS Mode
    5. 7.5 Register Maps
      1. 7.5.1  BIT Access Tag Conventions
      2. 7.5.2  Standard CSR Registers (address = 0x000 - 0x07)
        1. Table 6. Standard CSR Registers (0x000 - 0x07)
      3. 7.5.3  Standard CSR Register (address = 0x08)
        1. Table 7. Standard CSR Register (0x08)
      4. 7.5.4  Standard CSR Register (address = 0x09)
        1. Table 8. Standard CSR Register (0x09)
      5. 7.5.5  Standard CSR Register (address = 0x0A)
        1. Table 9. Standard CSR Register (0x0A)
      6. 7.5.6  Standard CSR Register (address = 0x0B)
        1. Table 10. Standard CSR Register (0x0B)
      7. 7.5.7  Standard CSR Register (address = 0x0D)
        1. Table 11. Standard CSR Register (0x0D)
      8. 7.5.8  Standard CSR Register (address = 0x0E)
        1. Table 12. Standard CSR Register (0x0E)
      9. 7.5.9  Standard CSR Register (address = 0x10) [reset = 0xFF]
        1. Table 13. Standard CSR Register (0x10)
      10. 7.5.10 Standard CSR Register (address = 0x11) [reset = 0xFF]
        1. Table 14. Standard CSR Register (0x11)
  8. 8 Application and Implementation
    1. 8.1 Application Information,
    2. 8.2 Typical Application, CSI-2 Implementations
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Reset Implementation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.3 TX Voltage Swing and Pre-Emphasis Control

In some applications, the DPHY440 may be placed at a location in the system where the channel from DPHY440 DB[3:0]P/N interface to the DPHY Sink (CSI-2 or DSI) is extremely long and the DPHY Sink does not have enough receive equalization to compensate for the ISI loss. In this application, the system architect may want to use the DPHY440 TX pre-emphasis feature to compensate for the lack of equalization at the DPHY sink. The DPHY440 provides two levels of pre-emphasis: 0 dB, and 2.5 dB. The TX Pre-emphasis settings is determined through the sampled sate of PRE_CFG[1:0] pins at the rising edge of RSTN. If necessary, the TX Pre-emphasis settings can be adjusted by writing to the HSTX_PRE register through the local I2C interface.

This feature must only be used when the HS pre-emphasis bit (transition bit) is attenuated by the channel. Enabling pre-emphasis in a system that has little channel loss (transition bit is not attenuated) may result in negative impact to system performance.

Table 3. HS Voltage Swing, HS Pre-emphasis, LPTX Edge Rate Controls

VSADJ_CFG0 PRE_CFG1 HS TX VOD HS TX PRE-EMPHASIS DB[3:0] LP TX RISE/FALL TIME
≤ VIL ≤ VIL 200 mV 0 dB 18 ns
VIM ≤ VIL 200 mV 0 dB 27 ns
≥ VIH ≤ VIL 220 mV 0 dB 18 ns
≤ VIL VIM 200 mV 0 dB 27 ns
VIM VIM 200 mV 0 dB 21 ns
≥ VIH VIM 220 mV 0 dB 21 ns
≤ VIL ≥ VIH 220 mV 2.5 dB 27 ns
VIM ≥ VIH 200 mV 2.5 dB 21 ns
≥ VIH ≥ VIH 220 mV 2.5 dB 21 ns