SLLSEB9F September   2012  – June 2018 SN65DSI85

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Typical Application
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Clock Configurations and Multipliers
      2. 8.3.2 ULPS
      3. 8.3.3 LVDS Pattern Generation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operating Modes
      2. 8.4.2 Reset Implementation
      3. 8.4.3 Initialization Sequence
      4. 8.4.4 LVDS Output Formats
      5. 8.4.5 DSI Lane Merging
      6. 8.4.6 DSI Pixel Stream Packets
      7. 8.4.7 DSI Video Transmission Specifications
    5. 8.5 Programming
      1. 8.5.1 Local I2C Interface Overview
    6. 8.6 Register Maps
      1. 8.6.1 Control and Status Registers Overview
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Video STOP and Restart Sequence
      2. 9.1.2 Reverse LVDS Pin Order Option
      3. 9.1.3 IRQ Usage
    2. 9.2 Typical Applications
      1. 9.2.1 Typical WUXGA 18-bpp Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Example Script
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Typical WQXGA 24-bpp Application
        1. 9.2.2.1 Design Requirements
  10. 10Power Supply Recommendations
    1. 10.1 VCC Power Supply
    2. 10.2 VCORE Power Supply
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Package Specific
      2. 11.1.2 Differential pairs
      3. 11.1.3 Ground
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

  • Implements MIPI® D-PHY Version 1.00.00 Physical Layer Front-End and Display Serial Interface (DSI) Version 1.02.00
  • Dual-Channel DSI Receiver Configurable for One, Two, Three, or Four D-PHY Data Lanes Per Channel Operating up to 1 Gbps Per Lane
  • Supports 18-bpp and 24-bpp DSI Video Packets with RGB666 and RGB888 Formats
  • Suitable for 60 fps WQXGA 2560 × 1600 Resolution at 18-bpp and 24-bpp Color, and WUXGA 1920 × 1200 Resolution with 3D Graphics at 60 fps (120 fps Equivalent)
  • MIPI® Front-End Configurable for Single-Channel or Dual-Channel DSI Configurations
  • FlatLink™ Output Configurable for Single-Link or Dual-Link LVDS
  • Supports Dual-Channel DSI ODD or EVEN and LEFT or RIGHT Operating Modes
  • Supports Two Single-Channel DSI to Two Single-Link LVDS Operating Mode
  • LVDS Output Clock Range of 25 MHz to 154 MHz in Dual-Link or Single-Link Mode
  • LVDS Pixel Clock May be Sourced from Free-Running Continuous D-PHY Clock or External Reference Clock (REFCLK)
  • 1.8-V Main VCC Power Supply
  • Low-Power Features Include SHUTDOWN Mode, Reduced LVDS Output Voltage Swing, Common Mode, and MIPI® Ultra-Low Power State (ULPS) Support
  • LVDS Channel SWAP, LVDS PIN Order Reverse Feature for Ease of PCB Routing
  • ESD Rating ±2 kV (HBM)
  • Packaged in 64-pin 5 mm x 5 mm BGA MICROSTAR JUNIOR (ZQE)
  • Temperature Range: –40°C to 85°C