SLLS889C June   2008  – August 2016 SN65HVD1040A-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Power Dissipation Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Operating Modes
        1. 9.3.1.1 Bus States by Mode
        2. 9.3.1.2 Normal Mode
        3. 9.3.1.3 Standby Mode and RXD Wake-Up Request
      2. 9.3.2 Protection Features
        1. 9.3.2.1 TXD Dominant State Time-Out
        2. 9.3.2.2 Thermal Shutdown
        3. 9.3.2.3 Undervoltage Lockout and Unpowered Device
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Using With 3.3-V Microcontrollers
      2. 10.1.2 Using SPLIT With Split Termination
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Bus Loading, Length, and Number of Nodes
        2. 10.2.1.2 CAN Termination
        3. 10.2.1.3 Loop Propagation Delay
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Transient Voltage Suppresser (TVS) Diodes
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 ESD Protection
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Community Resource
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
VCC Supply voltage –0.3 6 V
Voltage at bus terminals (CANH, CANL, SPLIT) –27 40 V
IO Receiver output current 20 mA
VI Voltage input, ISO 7637 transient pulse(3) (CANH, CANL) –150 100 V
VI Voltage input (TXD, STB) –0.3 6 V
TJ Junction temperature –40 150 °C
Tstg Storage temperature –40 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with ISO 7637 test pulses 1, 2, 3a, 3b per IBEE system level test (Pulse 1 = –100 V, Pulse 2 = 100 V, Pulse 3a = –150 V, Pulse 3b = 100 V). If dc may be coupled with AC transients, externally protect the bus pins within the absolute maximum voltage range at any bus terminal. This device has been tested with DC bus shorts to +40 V with leading common-mode chokes. If common-mode chokes are used in the system and the bus lines may be shorted to DC, ensure that the choke type and value in combination with the node termination and shorting voltage either does not create inductive flyback outside of voltage maximum specification or use an external transient-suppression circuit to protect the transceiver from the inductive transients.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) All pins except 5, 6, and 7 ±4000 V
Pins 6 and 7(2) ±12000
Pin 5(3) ±10000
Charged-device model (CDM), per AEC Q100-011 ±1500
Machine model (MM)(4) ±200
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(2) Test method based upon JEDEC Standard 22 Test Method A114F and AEC-Q100-002, CANH and CANL bus pins stressed with respect to each other and GND.
(3) Test method based upon JEDEC Standard 22 Test Method A114F and AEC-Q100-002, SPLIT pin stressed with respect to GND.
(4) Tested in accordance JEDEC Standard 22 Test Method A115A and AEC-Q100-003.

7.3 Recommended Operating Conditions

MIN MAX UNIT
VCC Supply voltage 4.75 5.25 V
VI or VIC Voltage at any bus terminal (separately or common mode) –12 12 V
VIH High-level input voltage TXD, STB 2 5.25 V
VIL Low-level input voltage TXD, STB 0 0.8 V
VID Differential input voltage –6 6 V
IOH High-level output current Driver –70 mA
Receiver (RXD) –2
IOL Low-level output current Driver 70 mA
Receiver (RXD) 2
TA Operating free-air temperature range See Thermal Information –40 125 °C
TJ Junction temperature –40 150 °C

7.4 Thermal Information

THERMAL METRIC(3) SN65HVD1040A-Q1 UNIT
D (SOIC)
8 PINS
RθJA Junction-to-ambient thermal resistance Low-K thermal resistance(1) 140 °C/W
High-K thermal resistance(2) 112 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 56 °C/W
RθJB Junction-to-board thermal resistance 50 °C/W
ψJT Junction-to-top characterization parameter 13 °C/W
ψJB Junction-to-board characterization parameter 55 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — °C/W
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, Low-K board, as specified in JESD51-3, in an environment described in JESD51-2a.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
(3) For more information about traditional and new thermal metrics, see the application report, Semiconductor and IC Package Thermal Metrics.

7.5 Electrical Characteristics

over recommended operating conditions including operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
SUPPLY
ICC 5-V supply current Standby mode STB at VCC, VI = VCC 6 12 µA
Dominant VI = 0 V, 60-Ω load, STB at 0 V 50 70 mA
Recessive VI = VCC, No load, STB at 0 V 6 10
UVVCC Undervoltage reset threshold 2.8 4 V
DRIVER
VO(D) Bus output voltage (dominant) CANH VI = 0 V, STB at 0 V, RL = 60 Ω,
See Figure 3 and Figure 15 		2.9 3.4 4.5 V
CANL 0.8 1.75
VO(R) Bus output voltage (recessive) VI = 3 V, STB at 0 V, RL = 60 Ω,
See Figure 3 and Figure 15 		2 2.5 3 V
VO Bus output voltage (standby mode) STB at Vcc, RL = 60 Ω,
See Figure 3 and Figure 15 		–0.1 0.1 V
VOD(D) Differential output voltage (dominant) VI = 0 V, RL = 60 Ω, STB at 0 V,
See Figure 3, Figure 15, and Figure 4 		1.5 3 V
VI = 0 V, RL = 45 Ω, STB at 0 V,
See Figure 3, Figure 15, and Figure 4 		1.4 3
VOD(R) Differential output voltage (recessive) VI = 3 V, STB at 0 V, RL = 60 Ω,
See Figure 3 and Figure 15 		–0.012 0.012 V
VI = 3 V, STB at 0 V, No load –0.5 0.05
VSYM Output symmetry (dominant or recessive) (VO(CANH) + VO(CANL)) STB at 0 V, RL = 60 Ω, See Figure 14 0.9 VCC VCC 1.1 VCC V
VOC(ss) Steady-state common-mode output voltage STB at 0 V, RL = 60 Ω, See Figure 9 2 2.5 3 V
ΔVOC(ss) Change in steady-state common-mode output voltage STB at 0 V, RL = 60 Ω, See Figure 9 30 mV
VIH High-level input voltage, TXD input 2 V
VIL Low-level input voltage, TXD input 0.8 V
IIH High-level input current, TXD input VI at VCC –2 2 µA
IIL Low-level input current, TXD input VI at 0 V –50 –10 µA
IO(off) Power-off TXD output current VCC at 0 V, TXD at 5 V 1 µA
IOS(ss) Short-circuit steady-state output current, Dominant VCANH = –12 V, CANL open, TXD = low,
See Figure 12 		–120 –85 mA
VCANH = 12 V, CANL open, TXD = low,
See Figure 12 		0.4 1
VCANL = –12 V, CANH open, TXD = low,
See Figure 12 		–1 –0.6
VCANL = 12 V, CANH open, TXD = low,
See Figure 12 		75 120
VCANH = 0 V, CANL open, TXD = low,
See Figure 12		 –100 –75
VCANL = 32 V, CANH open, , TXD = low,
See Figure 12		 75 125
IOS(ss) Short-circuit steady-state output current, Recessive –20 V ≤ VCANH ≤ 32 V, CANL open,
TXD = high, See Figure 12		 –10 10 mA
–20 V ≤ VCANL ≤ 32 V, CANH open,
TXD = high, See Figure 12		 –10 10
CO Output capacitance See receiver input capacitance
RECEIVER
VIT+ Positive-going input threshold voltage, high-speed mode STB at 0 V, See Table 1 800 900 mV
VIT– Negative-going input threshold voltage, high-speed mode STB at 0 V, See Table 1 500 650 mV
Vhys Hysteresis voltage (VIT+ – VIT–) 100 125 mV
VIT Input threshold voltage, standby mode STB at VCC 500 1150 mV
VOH High-level output voltage IO = –2 mA, See Figure 7 4 4.6 V
VOL Low-level output voltage IO = 2 mA, See Figure 7 0.2 0.4 V
II(off) Power-off bus input current (unpowered bus leakage current) CANH = CANL = 5 V,
VCC at 0 V, TXD at 0 V		 3 µA
IO(off) Power-off RXD leakage current VCC at 0 V, RXD at 5 V 20 µA
CI Input capacitance to ground (CANH or CANL) TXD at 3 V,
VI = 0.4 sin (4E6πt) + 2.5 V		 13 pF
CID Differential input capacitance TXD at 3 V, VI = 0.4 sin (4E6πt) 6 pF
RID Differential input resistance TXD at 3 V, STB at 0 V 30 80 kΩ
RIN Input resistance (CANH or CANL) TXD at 3 V, STB at 0 V 15 30 40 kΩ
RI(m) Input resistance matching
[1 – (RIN (CANH) / RIN (CANL))] × 100%		 V(CANH) = V(CANL) –3% 0% 3%
STB PIN
VIH High-level input voltage, STB input 2 V
VIL Low-level input voltage, STB input 0.8 V
IIH High-level input current STB at 2 V –10 0 µA
IIL Low-level input current STB at 0.8 V –10 0 µA
SPLIT PIN
VO Output voltage –500 µA < IO < 500 µA 0.3 × VCC 0.5 × VCC 0.7 × VCC V
IO(stb) Leakage current, standby mode STB at 2 V, –12 V ≤ VO ≤ 12 V –5 5 µA
(1) All typical values are at 25°C with a 5-V supply.

7.6 Power Dissipation Characteristics

over recommended operating conditions, TA = –40°C to 125°C (unless otherwise noted)
TEST CONDITIONS MIN TYP MAX UNIT
PD Average power dissipation VCC = 5 V, TJ = 27°C, RL = 60 Ω, STB at 0 V,
Input to TXD at 500 kHz, 50% duty cycle square wave, CL at RXD = 15 pF		 112 mW
VCC = 5.5 V, TJ = 130°C, RL = 45 Ω, STB at 0 V,
Input to TXD at 500 kHz, 50% duty cycle square wave, CL at RXD = 15 pF		 170
Thermal shutdown temperature 185 °C

7.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DEVICE SWITCHING CHARACTERISTICS
td(LOOP1) Total loop delay, driver input to receiver output, recessive to dominant STB at 0 V, see Figure 10 90 230 ns
td(LOOP2) Total loop delay, driver input to receiver output, dominant to recessive STB at 0 V, see Figure 10 90 230 ns
DRIVER SWITCHING CHARACTERISTICS
tPLH Propagation delay time, low-to-high level output STB at 0 V, see Figure 5 25 65 120 ns
tPHL Propagation delay time, high-to-low level output STB at 0 V, see Figure 5 25 45 120 ns
tr Differential output signal rise time STB at 0 V, see Figure 5 25 ns
tf Differential output signal fall time STB at 0 V, see Figure 5 45 ns
ten Enable time from standby mode to normal mode and transmission of dominant See Figure 8 10 µs
t(dom) Dominant time-out(1) ↓VI, see Figure 11 300 450 700 µs
RECEIVER SWITCHING CHARACTERISTICS
tPLH Propagation delay time, low-to-high-level output STB at 0 V , see Figure 7 60 90 130 ns
tPHL Propagation delay time, high-to-low-level output STB at 0 V , see Figure 7 45 70 130 ns
tr Output signal rise time STB at 0 V , see Figure 7 8 ns
tf Output signal fall time STB at 0 V , see Figure 7 8 ns
tBUS Dominant time required on bus for wakeup from standby STB at VCC, see Figure 13 1.5 5 µs
(1) The TXD dominant time-out (t(dom)) disables the driver of the transceiver once the TXD has been dominant longer than t(dom), which releases the bus lines to recessive, preventing a local failure from locking the bus dominant. The driver may only transmit dominant again after TXD has been returned HIGH (recessive). While this protects the bus from local faults, locking the bus dominant, it limits the minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst case, where 5 successive dominant bits are followed immediately by an error frame. This, along with the t(dom) minimum, limits the minimum bit rate. The minimum bit rate may be calculated by:
Minimum Bit Rate = 11/ t(dom) = 11 bits / 300 µs = 37 kbps

7.8 Typical Characteristics

SN65HVD1040A-Q1 D001_SLLS995.gif
Figure 1. Dominant Driver Differential Voltage
vs Free-Air Temperature
SN65HVD1040A-Q1 D002_SLLS995.gif
Figure 2. Driver Differential Voltage
vs Supply Voltage