The differential receivers of the SN65HVD147x family are failsafe to invalid bus states caused by the following:
In any of these cases, the differential receiver will output a failsafe logic high state so that the output of the receiver is not indeterminate.
Receiver failsafe is accomplished by offsetting the receiver thresholds such that the input indeterminate range does not include zero volts differential. In order to comply with the RS-422 and RS-485 standards, the receiver output must output a high when the differential input VID is more positive than 200 mV, and must output a Low when VID is more negative than –200 mV. The receiver parameters which determine the failsafe performance are VIT+, VIT–, and Vhys (the separation between VIT+ and VIT–). As shown in the Electrical Characteristics table, differential signals more negative than –200 mV will always cause a low receiver output, and differential signals more positive than 200 mV will always cause a high receiver output.
When the differential input signal is close to zero, it is still above the VIT+ threshold, and the receiver output will be High. Only when the differential input is more than Vhys below VIT+ will the receiver output transition to a Low state. Therefore, the noise immunity of the receiver inputs during a bus fault conditions includes the receiver hysteresis value, Vhys, as well as the value of VIT+.