8.3.1 Low-Power Standby Mode

When the driver and the receiver are both disabled (DE = Low and RE = High) the device enters standby mode. If the enable inputs are in the disabled state for only a brief time (for example: less than 100 ns), the device does not enter standby mode, preventing the SN65HVD888 from entering standby mode during driver or receiver enabling. Only when the enable inputs are held in the disabled state for a duration of 300 ns or more does the device enter low-power standby mode. In this mode most internal circuitry is powered down, and the steady-state supply current is typically less than 400 nA. When either the driver or the receiver is re-enabled, the internal circuitry becomes active. During V_CC power-up, when the device is set for both driver and receiver disabled mode, the device may consume more than 5-µA of I_CC disabled current because of capacitance charging effects. This condition occurs only during V_CC power up.

8.3.2 Bus Polarity Correction

The SN65HVD888 automatically corrects a wrong bus-signal polarity caused by a cross-wire fault. In order to detect the bus polarity, all three of the following conditions must be met:

• A failsafe-biasing network (commonly at the master node) must define the signal polarity of the bus
• A slave node must enable the receiver and disable the driver (RE = DE = Low)
• The bus must idle for the failsafe time, t_FS-max

After the failsafe time has passed, the polarity correction is complete and is applied to both the receive and transmit channels. The status of the bus polarity is latched within the transceiver and is maintained for subsequent data transmissions.

Figure 13 shows a simple point-to-point data link between a master node and a slave node. Because the master node with the failsafe biasing network determines the signal polarity on the bus, an RS-485 transceiver without polarity correction, such as SN65HVD82, suffices. All other bus nodes, typically performing as slaves, require the SN65HVD888 transceiver with polarity correction.

Figure 13. Point-To-Point Data Link With Cross-Wire Fault

Prior to initiating data transmission the master transceiver must idle for a time span that exceeds the maximum failsafe time, t_FS-max, of a slave transceiver. This idle time is accomplished by driving the direction control line, DIR, low. After a time, t > t_FS-max, the master begins transmitting data.

Because of the indicated cross-wire fault between master and slave, the slave node receives bus signals with reversed polarity. Assuming the slave node has just been connected to the bus, the direction-control pin is pulled-down during power-up and then is actively driven low by the slave MCU. The polarity correction begins as soon as the slave supply is established and ends after approximately 44 to 76 ms.

Figure 14. Polarity Correction Timing Prior to a Data Transmission

Initially the slave receiver assumes that the correct bus polarity is applied to the inputs and performs no polarity reversal. Because of the reversed polarity of the bus-failsafe voltage, the output of the slave receiver, R_S, turns low. After t_FS has passed and the receiver has detected the wrong bus polarity, the internal POLCOR logic reverses the input signal and R_S turns high.

At this point all incoming bus data with reversed polarity are polarity corrected within the transceiver. Because polarity correction is also applied to the transmit path, the data sent by the slave MCU are reversed by the POLCOR logic and then fed into the driver.

The reversed data from the slave MCU are reversed again by the cross-wire fault in the bus, and the correct bus polarity is reestablished at the master end.

This process repeats each time the device powers up and detects an incorrect bus polarity.

Table 1. Driver Pin Functions

Table 2. Receiver Pin Functions