SLLSFE2 June   2019 SN65HVDA1040B-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Power Dissipation Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Operating Modes
        1. 8.3.1.1 Bus States by Mode
        2. 8.3.1.2 Normal Mode
        3. 8.3.1.3 Standby Mode and RXD Wake-Up Request
      2. 8.3.2 Protection Features
        1. 8.3.2.1 TXD Dominant State Time-Out
        2. 8.3.2.2 Thermal Shutdown
        3. 8.3.2.3 Undervoltage Lockout and Unpowered Device
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Using With 3.3-V Microcontrollers
      2. 9.1.2 Using SPLIT With Split Termination
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Bus Loading, Length, and Number of Nodes
        2. 9.2.1.2 CAN Termination
        3. 9.2.1.3 Loop Propagation Delay
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Transient Voltage Suppresser (TVS) Diodes
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 ESD Protection
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DEVICE SWITCHING CHARACTERISTICS
td(LOOP1) Total loop delay, driver input to receiver output, recessive to dominant STB at 0 V, See Figure 10 90 230 ns
td(LOOP2) Total loop delay, driver input to receiver output, dominant to recessive STB at 0 V, See Figure 10 90 230 ns
DRIVER SWITCHING CHARACTERISTICS
tPLH Propagation delay time, low-to-high level output STB at 0 V, See Figure 5 25 65 120 ns
tPHL Propagation delay time, high-to-low level output STB at 0 V, See Figure 5 25 45 120 ns
tr Differential output signal rise time STB at 0 V, See Figure 5 25 ns
tf Differential output signal fall time STB at 0 V, See Figure 5 45 ns
ten Enable time from standby mode to normal mode and transmission of dominant See Figure 8 10 µs
t(dom) Dominant time-out(1) ↓VI, See Figure 11 300 450 700 µs
RECEIVER SWITCHING CHARACTERISTICS
tPLH Propagation delay time, low-to-high-level output STB at 0 V , See Figure 7 60 90 130 ns
tPHL Propagation delay time, high-to-low-level output STB at 0 V , See Figure 7 45 70 130 ns
tr Output signal rise time STB at 0 V , See Figure 7 8 ns
tf Output signal fall time STB at 0 V , See Figure 7 8 ns
tBUS Dominant time required on bus for wakeup from standby STB at VCC, See Figure 13 1 5 µs
(1) The TXD dominant time-out (t(dom)) disables the driver of the transceiver once the TXD has been dominant longer than t(dom), which releases the bus lines to recessive, preventing a local failure from locking the bus dominant. The driver may only transmit dominant again after TXD has been returned HIGH (recessive). While this protects the bus from local faults, locking the bus dominant, it limits the minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst case, where 5 successive dominant bits are followed immediately by an error frame. This, along with the t(dom) minimum, limits the minimum bit rate. The minimum bit rate may be calculated by:
Minimum Bit Rate = 11/ t(dom) = 11 bits / 300 µs = 37 kbps