SLLSEU5 December   2016 SN65LBC175A-EP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Designed for TIA/EIA-485, TIA/EIA-422 and
    ISO 8482 Applications
  • Signaling Rates (1) Exceeding 50 Mbps
  • Fail-Safe in Bus Short-Circuit, Open-Circuit, and Idle-Bus Conditions
  • ESD Protection on Bus Inputs Exceeds 6 kV
  • Common-Mode Bus Input Range –7 V to 12 V
  • Propagation Delay Times < 18 ns
  • Low Standby Power Consumption < 32 µA
  • Pin-Compatible Upgrade for MC3486, DS96F175, LTC489, and SN75175
The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
1. The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).

2 Applications

  • Supports Defense, Aerospace, and Medical Applications
    • Controlled Baseline
    • One Assembly and Test Site
    • One Fabrication Site
    • Extended Product Life Cycle
    • Extended Product-Change Notification
    • Product Traceability

3 Description

The SN65LBC175A-EP is a quadruple differential line receiver with 3-state outputs, designed for TIA/EIA-485 (RS-485), TIA/EIA-422 (RS-422), and ISO 8482 (Euro RS-485) applications.

This device is optimized for balanced multipoint bus communication at data rates up to and exceeding 50 million bits per second. The transmission media may be twisted-pair cables, printed-circuit board traces, or backplanes. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

The receiver operates over a wide range of positive and negative common-mode input voltages, and features ESD protection to 6 kV, making it suitable for high-speed multipoint data transmission applications in harsh environments. These devices are designed using LinBiCMOS®, facilitating low power consumption and robustness.

Two EN inputs provide pair-wise enable control, or these can be tied together externally to enable all four drivers with the same signal.

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Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
SN65LBC175A-EP SOIC (16) 9.90 mm × 3.90 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Logic Diagram

SN65LBC175A-EP logic_diagram_sllseu5.gif