SLLS573D December   2003  – December 2015 SN65MLVD200A , SN65MLVD202A , SN65MLVD204A , SN65MLVD205A


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics - Driver
    7. 7.7  Electrical Characteristics - Receiver
    8. 7.8  Electrical Characteristics - BUS Input and Output
    9. 7.9  Switching Characteristics - Driver
    10. 7.10 Switching Characteristics - Receiver
    11. 7.11 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power-On Reset
      2. 9.3.2 ESD Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device Function Tables
      2. 9.4.2 Equivalent Input and Output Schematic Diagrams
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1.  Supply Voltage
        2.  Supply Bypass Capacitance
        3.  Driver Input Voltage
        4.  Driver Output Voltage
        5.  Termination Resistors
        6.  Receiver Input Signal
        7.  Receiver Input Threshold (Failsafe)
        8.  Receiver Output Signal
        9.  Interconnecting Media
        10. PCB Transmission Lines
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Microstrip Versus Stripline Topologies
      2. 12.1.2 Dielectric Type and Board Construction
      3. 12.1.3 Recommended Stack Layout
      4. 12.1.4 Separation Between Traces
      5. 12.1.5 Crosstalk and Ground Bounce Minimization
      6. 12.1.6 Decoupling
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Related Links
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

12 Layout

12.1 Layout Guidelines

12.1.1 Microstrip Versus Stripline Topologies

According to the LVDS Application and Data Handbook (SLLD009), printed-circuit boards usually offer designers two transmission line options: microstrip and stripline. Microstrips are traces on the outer layer of a PCB, as shown in Figure 32.

SN65MLVD200A SN65MLVD202A SN65MLVD204A SN65MLVD205A lo_mt_sllsen0.png Figure 32. Microstrip Topology

Striplines are traces between two ground planes (see Figure 33). Striplines are less prone to emissions and susceptibility problems because the reference planes effectively shield the embedded traces. However, from the standpoint of high-speed transmission, juxtaposing two planes creates additional capacitance. TI recommends routing M-LVDS signals on microstrip transmission lines if possible. The PCB traces allow designers to specify the necessary tolerances for ZO based on the overall noise budget and reflection allowances. Footnotes 1(1), 2(2), and 3(3) provide the documentation for formulas for ZO and tPD for differential and single-ended traces.

(1) Howard Johnson and Martin Graham.1993. High Speed Digital Design – A Handbook of Black Magic. Prentice Hall PRT. ISBN number 013395724.
(2) Mark I. Montrose. 1996. Printed Circuit Board Design Techniques for EMC Compliance. IEEE Press. ISBN number 0780311310.
(3) Clyde F. Coombs. 1995. Printed Circuits Handbook. McGraw Hill. ISBN number 0070127549.

SN65MLVD200A SN65MLVD202A SN65MLVD204A SN65MLVD205A lo_st_sllsen0.png Figure 33. Stripline Topology

12.1.2 Dielectric Type and Board Construction

The speeds at which signals travel across the board dictates the choice of dielectric. FR-4, or equivalent, usually provides adequate performance for use with M-LVDS signals. If rise or fall times of TTL/CMOS signals are less than 500 ps, empirical results indicate that a material with a dielectric constant near 3.4, such as Rogers™ 4350 or Nelco N4000-13 is better suited. When the designer chooses the dielectric, there are several parameters pertaining to the board construction that can affect performance. The following set of guidelines were developed experimentally through several designs involving M-LVDS devices:

  • Copper weight: 15 g or ½ oz start, plated to 30 g or 1 oz
  • All exposed circuitry must be solder-plated (60/40) to 7.62 μm or 0.0003 in (minimum)
  • Copper plating must be 25.4 μm or 0.001 in (minimum) in plated-through-holes
  • Solder mask over bare copper with solder hot-air leveling

12.1.3 Recommended Stack Layout

Following the choice of dielectrics and design specifications, the designer must decide how many levels to use in the stack. To reduce the TTL/CMOS to M-LVDS crosstalk, it is a good practice to have at least two separate signal planes as shown in Figure 34.

SN65MLVD200A SN65MLVD202A SN65MLVD204A SN65MLVD205A lo_4lpcbb_sllsen0.gif Figure 34. Four-Layer PCB Board


The separation between layers 2 and 3 must be 127 μm (0.005 in). By keeping the power and ground planes tightly coupled, the increased capacitance acts as a bypass for transients.

One of the most common stack configurations is the six-layer board, as shown in Figure 35.

SN65MLVD200A SN65MLVD202A SN65MLVD204A SN65MLVD205A lo_6lpcbb_sllsen0.gif Figure 35. Six-Layer PCB Board

In this particular configuration, it is possible to isolate each signal layer from the power plane by at least one ground plane. The result is improved signal integrity; however, fabrication is more expensive. Using the 6-layer board is preferable because it offers the layout designer more flexibility in varying the distance between signal layers and referenced planes, in addition to ensuring reference to a ground plane for signal layers 1 and 6.

12.1.4 Separation Between Traces

The separation between traces depends on several factors; however, the amount of coupling that can be tolerated usually dictates the actual separation. Low-noise coupling requires close coupling between the differential pair of an M-LVDS link to benefit from the electromagnetic field cancellation. The traces must be
100-Ω differential and coupled in the manner that best fits this requirement. In addition, differential pairs must have the same electrical length to ensure that they are balanced, thus minimizing problems with skew and signal reflection.

In the case of two adjacent single-ended traces, one must use the 3-W rule, which stipulates that the distance between two traces must be greater than two times the width of one trace, or three times its width measured from trace center to trace center. This increased separation effectively reduces the potential for crosstalk. The same rule must be applied to the separation between adjacent M-LVDS differential pairs, whether the traces are edge-coupled or broad-side-coupled.

SN65MLVD200A SN65MLVD202A SN65MLVD204A SN65MLVD205A lo_3wrsedt_sllsen0.gif Figure 36. 3-W Rule for Single-Ended and Differential Traces (Top View)

Exercise caution when using autorouters because they do not always account for all factors affecting crosstalk and signal reflection. For instance, it is best to avoid sharp 90° turns to prevent discontinuities in the signal path. Using successive 45° turns tends to minimize reflections.

12.1.5 Crosstalk and Ground Bounce Minimization

To reduce crosstalk, it is important to provide a return path to high-frequency currents that is as close as possible to its originating trace. A ground plane usually achieves this. Because the returning currents always choose the path of lowest inductance, they are most likely to return directly under the original trace, thus minimizing crosstalk. Lowering the area of the current loop lowers the potential for crosstalk. Traces kept as short as possible with an uninterrupted ground plane running beneath them emit the minimum amount of electromagnetic field strength. Discontinuities in the ground plane increase the return path inductance and must be avoided.

12.1.6 Decoupling

Each power or ground lead of a high-speed device must be connected to the PCB through a low inductance path. For best results, one or more vias are used to connect a power or ground pin to the nearby plane. Ideally, via placement is immediately adjacent to the pin to avoid adding trace inductance. Placing a power plane closer to the top of the board reduces the effective via length and its associated inductance.

SN65MLVD200A SN65MLVD202A SN65MLVD204A SN65MLVD205A 12lpcb_sllsen0.gif Figure 37. Low Inductance, High-Capacitance Power Connection

Bypass capacitors must be placed close to VDD pins and can be placed conveniently near the corners or underneath the package to minimize the loop area. This extends the useful frequency range of the added capacitance. Small physical-size capacitors (such as 0402, 0201, or X7R surface-mount capacitors) must be used to minimize body inductance of capacitors. Each bypass capacitor is connected to the power and ground plane through vias tangent to the pads of the capacitor as shown in Figure 38(a).

An X7R surface-mount capacitor of size 0402 has about 0.5 nH of body inductance. At frequencies above about 30 MHz, X7R capacitors behave as low-impedance inductors. To extend the operating frequency range to a few hundred MHz, an array of different capacitor values like 100 pF, 1 nF, 0.03 μF, and 0.1 μF are commonly used in parallel. The most effective bypass capacitor can be built using sandwiched layers of power and ground at a separation of 2 to 3 mils. With a 2-mil FR4 dielectric, there is approximately 500 pF per square inch of PCB.

Many high-speed devices provide a low-inductance GND connection on the backside of the package. This center pad must be connected to a ground plane through an array of vias. The via array reduces the effective inductance to ground and enhances the thermal performance of the small surface mount technology (SMT) package. Placing vias around the perimeter of the pad connection ensures proper heat spreading and the lowest possible die temperature. Placing high-performance devices on opposing sides of the PCB using two GND planes (as shown in Figure 29) creates multiple paths for heat transfer.

Thermal PCB issues are often the result of one device adding heat to another, resulting in a very high local temperature. Multiple paths for heat transfer minimize this possibility. In many cases, the GND pad that is so important for heat dissipation makes the optimal decoupling layout impossible to achieve, due to insufficient pad-to-pad spacing as shown in Figure 39(b). When this occurs, placing the decoupling capacitor on the backside of the board keeps the extra inductance to a minimum.

It is important to place the VDD via as close to the device pin as possible while still allowing for sufficient solder mask coverage. If the via is left open, solder may flow from the pad into the via barrel, which results in a poor solder connection

SN65MLVD200A SN65MLVD202A SN65MLVD204A SN65MLVD205A typ_decoupling_cap_layout_A_slls573.gif Figure 38. Typical Decoupling Capacitor Layout (a)
SN65MLVD200A SN65MLVD202A SN65MLVD204A SN65MLVD205A typ_decoupling_cap_layout_B_slls573.gif Figure 39. Typical Decoupling Capacitor Layout (b)

12.2 Layout Example

At least two or three times the width of an individual trace must separate single-ended traces and differential pairs to minimize the potential for crosstalk. Single-ended traces that run in parallel for less than the wavelength of the rise or fall times usually have negligible crosstalk. Increase the spacing between signal paths for long parallel runs to reduce crosstalk. Boards with limited real estate can benefit from the staggered trace layout, as shown in Figure 40.

SN65MLVD200A SN65MLVD202A SN65MLVD204A SN65MLVD205A lo_stl_sllsen0.gif Figure 40. Staggered Trace Layout

This configuration lays out alternating signal traces on different layers; thus, the horizontal separation between traces can be less than 2 or 3 times the width of individual traces. To ensure continuity in the ground signal path, TI recommends having an adjacent ground via for every signal via, as shown in Figure 41.


Vias create additional capacitance. For example, a typical via has a lumped capacitance effect of ½ pF to 1 pF in FR4.

SN65MLVD200A SN65MLVD202A SN65MLVD204A SN65MLVD205A lo_gvasv_sllsen0.gif Figure 41. Ground Via Location (Side View)

Short and low-impedance connection of the device ground pins to the PCB ground plane reduces ground bounce. Holes and cutouts in the ground planes can adversely affect current return paths if they create discontinuities that increase returning current loop areas.

To minimize EMI problems, TI recommends avoiding discontinuities below a trace (for example, holes, slits, and so on) and keeping traces as short as possible. Zoning the board wisely by placing all similar functions in the same area, as opposed to mixing them together, helps reduce susceptibility issues.