SLLS573D December   2003  – December 2015 SN65MLVD200A , SN65MLVD202A , SN65MLVD204A , SN65MLVD205A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics - Driver
    7. 7.7  Electrical Characteristics - Receiver
    8. 7.8  Electrical Characteristics - BUS Input and Output
    9. 7.9  Switching Characteristics - Driver
    10. 7.10 Switching Characteristics - Receiver
    11. 7.11 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power-On Reset
      2. 9.3.2 ESD Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device Function Tables
      2. 9.4.2 Equivalent Input and Output Schematic Diagrams
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1  Supply Voltage
        2. 10.2.2.2  Supply Bypass Capacitance
        3. 10.2.2.3  Driver Input Voltage
        4. 10.2.2.4  Driver Output Voltage
        5. 10.2.2.5  Termination Resistors
        6. 10.2.2.6  Receiver Input Signal
        7. 10.2.2.7  Receiver Input Threshold (Failsafe)
        8. 10.2.2.8  Receiver Output Signal
        9. 10.2.2.9  Interconnecting Media
        10. 10.2.2.10 PCB Transmission Lines
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Microstrip Versus Stripline Topologies
      2. 12.1.2 Dielectric Type and Board Construction
      3. 12.1.3 Recommended Stack Layout
      4. 12.1.4 Separation Between Traces
      5. 12.1.5 Crosstalk and Ground Bounce Minimization
      6. 12.1.6 Decoupling
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Related Links
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Low-Voltage Differential 30-Ω to 55-Ω Line Drivers and Receivers for Signaling Rates(1) up to
    100 Mbps, Clock Frequencies up to 50 MHz
  • Type-1 Receivers Incorporate 25 mV of Hysteresis (SN65MLVD200A, SN65MLVD202A)
  • Type-2 Receivers Provide an Offset (100 mV) Threshold to Detect Open-Circuit and Idle-Bus Conditions (SN65MLVD204A, SN65MLVD205A)
  • Meets or Exceeds the M-LVDS Standard
    TIA/EIA-899 for Multipoint Data Interchange
  • Controlled Driver Output Voltage Transition Times for Improved Signal Quality
  • –1 V to 3.4 V of Common-Mode Voltage Range Allows Data Transfer With 2 V of Ground Noise
  • Bus Pins High Impedance When Disabled
    or VCC ≤ 1.5 V
  • 200-Mbps Devices Available (SN65MLVD201, SN65MLVD203, SN65MLVD206, SN65MLVD207)
  • Bus Pin ESD Protection Exceeds 8 kV
  • Packages Available:
    • 8-Pin SOIC
      SN65MLVD200A, SN65MLVD204A
    • 14-Pin SOIC
      SN65MLVD202A, SN65MLVD205A
  • Improved Alternatives to the SN65MLVD200, SN65MLVD202A, SN65MLVD204A, and SN65MLVD205A Devices (1)
(1) The signaling rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second).

2 Applications

  • Low-Power, High-Speed, Short-Reach Alternative to TIA/EIA-485
  • Backplane or Cabled Multipoint Data and Clock Transmission
  • Cellular Base Stations
  • Central Office Switches
  • Network Switches and Routers

3 Description

The SN65MLVD20xx devices are multipoint low-voltage differential (M-LVDS) line drivers and receivers that are optimized to operate at signaling rates up to 100 Mbps. All parts comply with the multipoint low-voltage differential signaling (M-LVDS) standard TIA/EIA-899.

The SN65MLVD20xx devices have enhancements over their predecessors. Improved features include controlled slew rate on the driver output to help minimize reflections from unterminated stubs, which results in better signal integrity. Additionally, 8-kV ESD protection on the bus pins for more robustness. The same footprint definition was maintained making for an easy drop-in replacement for a system performance upgrade.

The devices are characterized for operation from –40°C to 85°C.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
SN65MLVD200A SOIC (8) 4.90 mm × 3.91 mm
SN65MLVD204A
SN65MLVD202A SOIC (14) 8.65 mm × 3.91 mm
SN65MLVD205A
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Logic Diagrams (Positive Logic)

SN65MLVD200A SN65MLVD202A SN65MLVD204A SN65MLVD205A log_dig_lls573.gif