SLLS573D December   2003  – December 2015 SN65MLVD200A , SN65MLVD202A , SN65MLVD204A , SN65MLVD205A

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics - Driver
    7. 7.7  Electrical Characteristics - Receiver
    8. 7.8  Electrical Characteristics - BUS Input and Output
    9. 7.9  Switching Characteristics - Driver
    10. 7.10 Switching Characteristics - Receiver
    11. 7.11 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power-On Reset
      2. 9.3.2 ESD Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device Function Tables
      2. 9.4.2 Equivalent Input and Output Schematic Diagrams
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1  Supply Voltage
        2. 10.2.2.2  Supply Bypass Capacitance
        3. 10.2.2.3  Driver Input Voltage
        4. 10.2.2.4  Driver Output Voltage
        5. 10.2.2.5  Termination Resistors
        6. 10.2.2.6  Receiver Input Signal
        7. 10.2.2.7  Receiver Input Threshold (Failsafe)
        8. 10.2.2.8  Receiver Output Signal
        9. 10.2.2.9  Interconnecting Media
        10. 10.2.2.10 PCB Transmission Lines
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Microstrip Versus Stripline Topologies
      2. 12.1.2 Dielectric Type and Board Construction
      3. 12.1.3 Recommended Stack Layout
      4. 12.1.4 Separation Between Traces
      5. 12.1.5 Crosstalk and Ground Bounce Minimization
      6. 12.1.6 Decoupling
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Related Links
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Parameter Measurement Information

SN65MLVD200A SN65MLVD202A SN65MLVD204A SN65MLVD205A pm_drive1_lls573.gif Figure 13. Driver Voltage and Current Definitions
SN65MLVD200A SN65MLVD202A SN65MLVD204A SN65MLVD205A pm_diff2_lls573.gif
A. All resistors are 1% tolerance.
Figure 14. Differential Output Voltage Test Circuit
SN65MLVD200A SN65MLVD202A SN65MLVD204A SN65MLVD205A pm_test3_lls573.gif
A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns,
pulse frequency = 1 MHz, duty cycle = 50 ± 5%.
B. C1, C2 and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
C. R1 and R2 are metal film, surface mount, ±1%, and located within 2 cm of the D.U.T.
D. The measurement of VOS(PP) is made on test equipment with a –3 dB bandwidth of at least 1 GHz.
Figure 15. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
SN65MLVD200A SN65MLVD202A SN65MLVD204A SN65MLVD205A pm_drive4_lls573.gif Figure 16. Driver Short-Circuit Test Circuit
SN65MLVD200A SN65MLVD202A SN65MLVD204A SN65MLVD205A pm_drive5_lls573.gif
A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, frequency = 1 MHz, duty cycle = 50 ± 5%.
B. C1, C2, and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
C. R1 is a metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.
D. The measurement is made on test equipment with a –3 dB bandwidth of at least 1 GHz.
Figure 17. Driver Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
SN65MLVD200A SN65MLVD202A SN65MLVD204A SN65MLVD205A pm_drive6_lls573.gif
A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, frequency = 1 MHz, duty cycle = 50 ± 5%.
B. C1, C2, C3, and C4 includes instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
C. R1 and R2 are metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.
D. The measurement is made on test equipment with a –3 dB bandwidth of at least 1 GHz.
Figure 18. Driver Enable and Disable Time Circuit and Definitions
SN65MLVD200A SN65MLVD202A SN65MLVD204A SN65MLVD205A pm_max7_lls573.gif Figure 19. Maximum Steady State Output Voltage
SN65MLVD200A SN65MLVD202A SN65MLVD204A SN65MLVD205A pm_drive8_lls573.gif
A. All input pulses are supplied by an Agilent 81250 Stimulus System.
B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software
C. Period jitter is measured using a 50 MHz 50 ±1% duty cycle clock input.
D. Peak-to-peak jitter is measured using a 100 Mbps 215 –1 PRBS input.
Figure 20. Driver Jitter Measurement Waveforms
SN65MLVD200A SN65MLVD202A SN65MLVD204A SN65MLVD205A pm_rec9_lls573.gif Figure 21. Receiver Voltage and Current Definitions

Table 1. Type-1 Receiver Input Threshold Test Voltages

APPLIED VOLTAGES RESULTING DIFFERENTIAL
INPUT VOLTAGE
RESULTING COMMON-
MODE INPUT VOLTAGE
RECEIVER
(1)OUTPUT
VIA VIB VID VIC
2.400 0.000 2.400 1.200 H
0.000 2.400 –2.400 1.200 L
3.425 3.335 0.050 3.4 H
3.375 3.425 –0.050 3.4 L
–0.975 –1.025 0.050 –1 H
–1.025 –0.975 –0.050 –1 L
(1) H= high level, L = low level, output state assumes receiver is enabled (RE = L)

Table 2. Type-2 Receiver Input Threshold Test Voltages

APPLIED VOLTAGES RESULTING DIFFERENTIAL
INPUT VOLTAGE
RESULTING COMMON-
MODE INPUT VOLTAGE
RECEIVER
OUTPUT(1)
VIA VIB VID VIC
2.400 0.000 2.400 1.200 H
0.000 2.400 –2.400 1.200 L
3.475 3.325 0.150 3.4 H
3.425 3.375 0.050 3.4 L
–0.925 –1.075 0.150 –1 H
–0.975 –1.025 0.050 –1 L
(1) H= high level, L = low level, output state assumes receiver is enabled (RE = L)
SN65MLVD200A SN65MLVD202A SN65MLVD204A SN65MLVD205A pm_rec10_lls573.gif
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 1 MHz, duty cycle = 50 ± 5%. CL is a combination of a 20%-tolerance, low-loss ceramic, surface-mount capacitor and fixture capacitance within 2 cm of the D.U.T.
B. The measurement is made on test equipment with a –3 dB bandwidth of at least 1 GHz.
Figure 22. Receiver Timing Test Circuit and Waveforms
SN65MLVD200A SN65MLVD202A SN65MLVD204A SN65MLVD205A pm_rec11_lls573.gif
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 1 MHz, duty cycle = 50 ± 5%.
B. RL is 1% tolerance, metal film, surface mount, and located within 2 cm of the D.U.T.
C. CL is the instrumentation and fixture capacitance within 2 cm of the DUT and ±20%.
Figure 23. Receiver Enable and Disable Time Test Circuit and Waveforms
SN65MLVD200A SN65MLVD202A SN65MLVD204A SN65MLVD205A pm_rec12_lls573.gif
A. All input pulses are supplied by an Agilent 8304A Stimulus System.
B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software
C. Period jitter is measured using a 50 MHz 50 ±1% duty cycle clock input.
D. Peak-to-peak jitter is measured using a 100 Mbps 215 –1 PRBS input.
Figure 24. Receiver Jitter Measurement Waveforms