SCES551E February   2004  – November 2015 SN74AVC16T245

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Switching Characteristics: VCCA = 1.2 V
    7. 7.7  Switching Characteristics: VCCA = 1.5 V ± 0.1 V
    8. 7.8  Switching Characteristics: VCCA = 1.8 V ± 0.15 V
    9. 7.9  Switching Characteristics: VCCA = 2.5 V ± 0.2 V
    10. 7.10 Switching Characteristics: VCCA = 3.3 V ± 0.3 V
    11. 7.11 Operating Characteristics
    12. 7.12 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.2-V to 3.6-V Power-Supply Range
      2. 9.3.2 Partial-Power-Down Mode Operation
      3. 9.3.3 VCC Isolation
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Enable Times
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Input Voltage Ranges
        2. 10.2.2.2 Output Voltage Range
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

10.1 Application Information

The SN74AVC16T245 device can be used in level-shifting applications for interfacing devices and addressing mixed voltage incompatibility. The SN74AVC16T245 device is ideal for data transmission where direction is different for each channel.

10.1.1 Enable Times

Calculate the enable times for the SN74AVC16T45 using the following formulas:

Equation 1. tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A)
Equation 2. tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A)
Equation 3. tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B)
Equation 4. tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B)

In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is switched until an output is expected. For example, if the SN74AVC16T245 initially is transmitting from A to B, then the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified propagation delay.

10.2 Typical Application

SN74AVC16T245 typapp_sces551.gif Figure 12. Typical Application Schematic

10.2.1 Design Requirements

This device uses drivers which are enabled depending on the state of the DIR pin. The designer must know the intended flow of data and take care not to violate any of the high or low logic levels. Unused data inputs must not be floating, as this can cause excessive internal leakage on the input CMOS structure. Tie any unused input and output ports directly to ground.

For this design example, use the parameters listed in Table 2.

Table 2. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
Input voltage range 1.2 V to 3.6 V
Output voltage range 1.2 V to 3.6 V

10.2.2 Detailed Design Procedure

To begin the design process, determine the following:

10.2.2.1 Input Voltage Ranges

Use the supply voltage of the device that is driving the SN74AVC16T245 device to determine the input voltage range. For a valid logic high the value must exceed the VIH of the input port. For a valid logic low the value must be less than the VIL of the input port.

10.2.2.2 Output Voltage Range

Use the supply voltage of the device that the SN74AVC16T245 device is driving to determine the output voltage range.

10.2.3 Application Curve

SN74AVC16T245 translation_up_1_2_V_to_3_3_V_sces551.gif Figure 13. Translation Up (1.2 V to 3.3 V) at 2.5 MHz