SCES908A February   2020  – April 2020 SN74AXC2T245-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Functional Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics, VCCA = 0.7 ± 0.05 V
    7. 6.7  Switching Characteristics, VCCA = 0.8 ± 0.04 V
    8. 6.8  Switching Characteristics, VCCA = 0.9 ± 0.045 V
    9. 6.9  Switching Characteristics, VCCA = 1.2 ± 0.1 V
    10. 6.10 Switching Characteristics, VCCA = 1.5 ± 0.1 V
    11. 6.11 Switching Characteristics, VCCA = 1.8 ± 0.15 V
    12. 6.12 Switching Characteristics, VCCA = 2.5 ± 0.2 V
    13. 6.13 Switching Characteristics, VCCA = 3.3 ± 0.3 V
    14. 6.14 Operating Characteristics: TA = 25°C
  7. 7 Parameter Measurement Information
    1. 7.1 Load Circuit and Voltage Waveforms
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Standard CMOS Inputs
      2. 8.3.2 Balanced High-Drive CMOS Push-Pull Outputs
      3. 8.3.3 Partial Power Down (Ioff)
      4. 8.3.4 VCC Isolation
      5. 8.3.5 Over-voltage Tolerant Inputs
      6. 8.3.6 Glitch-free Power Supply Sequencing
      7. 8.3.7 Negative Clamping Diodes
      8. 8.3.8 Fully Configurable Dual-Rail Design
      9. 8.3.9 Supports High-Speed Translation
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.1 Load Circuit and Voltage Waveforms

Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:

  • f = 1 MHz
  • ZO = 50 Ω
  • dv/dt ≤ 1 ns/V

SN74AXC2T245-Q1 SN74AXC1T45_PMI_DIAGRAM.gif
1. CL includes probe and jig capacitance.
Figure 1. Load Circuit

Table 1. Load Circuit Conditions

Parameter VCCO RL CL S1 VTP
Δt/Δv Input transition rise or fall rate 0.65 V – 3.6 V 1 MΩ 15 pF Open N/A
tpd Propagation (delay) time 1.1 V – 3.6 V 2 kΩ 15 pF Open N/A
0.65 V – 0.95 V 20 kΩ 15 pF Open N/A
ten, tdis Enable time, disable time 3 V – 3.6 V 2 kΩ 15 pF 2 × VCCO 0.3 V
1.65 V – 2.7 V 2 kΩ 15 pF 2 × VCCO 0.15 V
1.1 V – 1.6 V 2 kΩ 15 pF 2 × VCCO 0.1 V
0.65 V – 0.95 V 20 kΩ 15 pF 2 × VCCO 0.1 V
ten, tdis Enable time, disable time 3 V – 3.6 V 2 kΩ 15 pF GND 0.3 V
1.65 V – 2.7 V 2 kΩ 15 pF GND 0.15 V
1.1 V – 1.6 V 2 kΩ 15 pF GND 0.1 V
0.65 V – 0.95 V 20 kΩ 15 pF GND 0.1 V
SN74AXC2T245-Q1 SN74AXC1T45_PMI_DIAGRAM2.gif
  1. VCCI is the supply pin associated with the input port.
  2. VOH and VOL are typical output voltage levels that occur with specified RL, CL, and S1
Figure 2. Propagation Delay
SN74AXC2T245-Q1 SN74AXC1T45_PMI_DIAGRAM4.gif
  1. VCCI is the supply pin associated with the input port.
  2. VOH and VOL are typical output voltage levels that occur with specified RL, CL, and S1
Figure 3. Input Transition Rise or Fall Rate
SN74AXC2T245-Q1 SN74AXC8T245_ENABLE_TIME_AND_DISABLE_TIME.gif
1. Output waveform on the condition that input is driven to a valid Logic Low.
2. Output waveform on the condition that input is driven to a valid Logic High.
3. VCCO is the supply pin associated with the output port.
4. VOH and VOL are typical output voltage levels with specified RL, CL, and S1.
Figure 4. Enable Time And Disable Time