SCLS136F December   1982  – April 2022 SN54HC273 , SN74HC273

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings – SN74HC273
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Electrical Characteristics – SN54HC273
    7. 6.7  Electrical Characteristics – SN74HC273
    8. 6.8  Timing Requirements
    9. 6.9  Timing Requirements – SN54HC273
    10. 6.10 Timing Requirements – SN74HC273
    11. 6.11 Switching Characteristics
    12. 6.12 Switching Characteristics – SN54HC273
    13. 6.13 Switching Characteristics – SN74HC273
    14. 6.14 Operating Characteristics
    15. 6.15 Typical Characteristics
  7. 7 Parameter Measurement Information
    1.     23
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DB|20
  • NS|20
  • N|20
  • DW|20
  • PW|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The SNx4HC273 devices are positive-edge-triggered D-type flip-flops with a direct active low clear ( CLR) input.

Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.

Device Information(1)
PART NUMBERPACKAGE (PINS)BODY SIZE (NOM)
SN54HC273JCDIP (20)24.20 mm × 6.92 mm
SN54HC273WCFP (20)13.09 mm × 6.92 mm
SN54HC273FKLCCC (20)8.89 mm × 8.89 mm
SN74HC273DSOIC (20)12.80 mm × 7.50 mm
SN74HC273DBSSOP (20)7.20 mm × 5.30 mm
SN74HC273NSSO (20)12.60 mm × 5.30 mm
SN74HC273NPDIP (20)24.33 mm × 6.35 mm
SN74HC273PWTSSOP (20)6.50 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-0A1AB7E1-4E85-4DC3-AD4D-499403CE0B52-low.gif Functional Block Diagram