SCLS807E june   2020  – july 2023 SN74HCS594-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Operating Characteristics
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Balanced CMOS Push-Pull Outputs
      2. 8.3.2 CMOS Schmitt-Trigger Inputs
      3. 8.3.3 Clamp Diode Structure
      4. 8.3.4 Wettable Flanks
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Power Considerations
        2. 9.2.1.2 Input Considerations
        3. 9.2.1.3 Output Considerations
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-0BF64138-AA99-4467-86A9-548B304BB95C-low.gifD, PW, or DYY Package,
16-Pin SOIC, TSSOP, or SOT
(Top View)
GUID-20200820-CA0I-LVGW-LJH3-D3KLRXHXFLJQ-low.gifBQB or WBQB Package,
16-Pin WQFN
(Top View)
Pin Functions
PIN TYPE(2) DESCRIPTION
NAME NO.
QB 1 O QB output
QC 2 O QC output
QD 3 O QD output
QE 4 O QE output
QF 5 O QF output
QG 6 O QG output
QH 7 O QH output
GND 8 — Ground
QH' 9 O Serial output, can be used for cascading
SRCLR 10 I Shift register clear, active low
SRCLK 11 I Shift register clock, rising edge triggered
RCLK 12 I Output register clock, rising edge triggered
RCLR 13 I Storage register clear, active low
SER 14 I Serial input
QA 15 O QA output
VCC 16 — Positive supply
Thermal Pad(1) — The thermal pad can be connected to GND or left floating. Do not connect to any other signal or supply.
(1) BQB and WBQB Package, only.
(2) I = input, O = output