SDLS146B October   1976  – September 2016 SN54LS245 , SN74LS245

 

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 3-State outputs
      2. 9.3.2 PNP Inputs
      3. 9.3.3 Hysteresis on Bus Inputs
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resource
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DB|20
  • NS|20
  • N|20
  • DW|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • 3-State Outputs Drive Bus Lines Directly
  • PNP Inputs Reduce DC Loading on Bus Lines
  • Hysteresis at Bus Inputs Improves Noise Margins
  • Typical Propagation Delay Times Port to Port,
    8 ns

2 Applications

  • Building Automation
  • Electronic Point of Sale
  • Factory Automation and Control
  • Test and Measurement

3 Description

These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.

The SNx4LS245 devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can disable the device so that the buses are effectively isolated.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
SN54LS245J CDIP (20) 24.20 mm × 6.92 mm
SN54LS245W CFP (20) 7.02 mm × 13.72 mm
SN54LS245FK LCCC (20) 8.89 mm × 8.89 mm
SN74LS245DB SSOP (20) 7.20 mm × 5.30 mm
SN74LS245DW SOIC (20) 12.80 mm × 7.50 mm
SN74LS245N PDIP (20) 24.33 mm × 6.35 mm
SN74LS245NS SO (20) 12.60 mm × 5.30 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Logic Diagram (Positive Logic)

SN54LS245 SN74LS245 logic_dls146.gif