SCLS741C November   2013  – October 2023 SN74LV1T32

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 5
  6. 5 Related Products
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Operating Characteristics
    8. 7.8 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Clamp Diode Structure
      2. 9.3.2 Balanced CMOS Push-Pull Outputs
      3. 9.3.3 LVxT Enhanced Input Voltage
        1. 9.3.3.1 Down Translation
        2. 9.3.3.2 Up Translation
    4. 9.4 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Power Supply Recommendations
    2. 10.2 Layout
      1. 10.2.1 Layout Guidelines
        1. 10.2.1.1 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support (Analog)
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Related Products

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SN74LV1T08 DCK, DBV 2-Input Positive-AND Gate
SN74LV1T17 DCK, DBV Single Schmitt-Trigger Buffer Gate
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SN74LV1T32 DCK, DBV 2-Input Positive-OR Gate
SN74LV1T34 DCK, DBV Single Buffer Gate
SN74LV1T86 DCK, DBV Single 2-Input Exclusive-Or Gate
SN74LV1T125 DCK, DBV Single Buffer Gate with 3-state Output
SN74LV1T126 DCK, DBV Single Buffer Gate with 3-state Output
SN74LV4T125 RGY, PW Quadruple Bus Buffer Gate With 3-State Outputs