SCLS429K MAY   1999  – November 2016 SN74LV4052A

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics: VCC = 2.5 V ± 0.2 V
    7. 6.7  Switching Characteristics: VCC = 3.3 V ± 0.3 V
    8. 6.8  Switching Characteristics: VCC = 5 V ± 0.5 V
    9. 6.9  Switching Characteristics: Analog
    10. 6.10 Operating Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resource
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DB|16
  • PW|16
  • NS|16
  • N|16
  • RGY|16
  • D|16
  • DGV|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

The SN74LV4052A device is a dual, 4-channel CMOS analog multiplexer and demultiplexer that is designed for 2-V to 5.5-V VCC operation. It has low input current consumption at the digital input pins and low crosstalk between switches. The active low Inhibit (INH) tri-state all the channels when high and when low, depending on the A and B inputs, one of the four independent input/outputs (nY0 - nY3) connects to the COM channel. The SN74LV4052A is available in multiple package options including TSSOP (PW) and QFN (RGY).

8.2 Functional Block Diagram

SN74LV4052A ld_cls429.gif Figure 12. Logic Diagram (Positive Logic)

8.3 Feature Description

  • The SN74LV4052A operates from 2-V to 5.5-V VCC with extremely low input current consumption at the CMOS input pins of A, B and INH.
  • The SN74LV4052A enables fast switching with low crosstalk between the switches. 5.5 V peak level bidirectional transmission allowed with the either analog or digital signals.

8.4 Device Functional Modes

Table 1 lists the functional modes of SN74LV4052A.

Table 1. Function Table

INPUTS ON
CHANNELS
INH B A
L L L 1Y0, 2Y0
L L H 1Y1, 2Y1
L H L 1Y2, 2Y2
L H H 1Y3, 2Y3
H X X None