SCLS749B February   2014  – September 2014 SN74LV4T125

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Simplified Application Diagram
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Noise Characteristics
    8. 7.8 Operating Characteristics
    9. 7.9 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Translating Down
      2. 9.1.2 Translating Up
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Additional Product Selection
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Detailed Description

9.1 Overview

The SN74LVxTxx family was created to allow up- or down-voltage translation with only one power rail. The family has over-voltage tolerant inputs that allow down translation from up to 5.5 V to the VCC level that can be as low as 1.8 V. The family SN74LVxTxx also has a lowered switching threshold that allows it to translate up to the VCC level that can be as high as 5.5 V.

9.1.1 Translating Down

Using these parts to translate down is very simple. Because the inputs are tolerant to 5.5 V at any valid VCC, they can be used to down translate. The input can be any level above VCC up to 5.5 V and the output will equal the VCC level, which can be as low as 1.8 V. One important advantage to down translating using this part is that the ICC current will remain less than or equal to the specified value.

Down translation possibilities with SN74LVxTxx:

  • With 1.8-V VCC from 2.5 V, 3.3 V, or 5 V down to 1.8 V.
  • With 2.5-V VCC from 3.3 V or 5 V down to 2.5 V.
  • With 3.3-V VCC from 5 V down to 3.3 V.

9.1.2 Translating Up

Using the SN74LVxTxx family to translate up is very simple. The input switching threshold is lowered so the high level of the input voltage can be much lower than a typical CMOS VIH. For instance, If the VCC is 3.3 V then the typical CMOS switching threshold would be VCC / 2 or 1.65 V. This means the input high level must be at least VCC × 0.7 or 2.31 V. On the LVxT devices the input threshold for 3.3-V VCC is approximately 1 V. This allows a signal with a 1.8-V VIH to be translated up to the VCC level of 3.3 V.

Up translation possibilities with SN74LVxTxx:

  • With 2.5-V VCC from 1.8 V to 2.5 V.
  • With 3.3-V VCC from 1.8 V or 2.5 V to 3.3 V.
  • With 5-V VCC From 2.5 V or 3.3 V to 5 V.

9.2 Functional Block Diagram

logic_SCLS749.gif

9.3 Feature Description

This part is a single supply buffer that is capable up or down translation. The output will equal VCC while the input can vary from 1.2 V to 5.5 V.

Up Translation Mode:

  • 1.2 V to 1.8 V at 1.8-V VCC
  • 1.5 V to 2.5 V at 2.5-V VCC
  • 1.8 V to 3.3 V at 3.3-V VCC
  • 3.3 V to 5.0 V at 5.0-V VCC

Down Translation Mode:

  • 3.3 V to 1.8 V at 1.8-V VCC
  • 3.3 V to 2.5 V at 2.5-V VCC
  • 5.0 V to 3.3 V at 3.3-V VCC

9.4 Device Functional Modes

This device performs the function of a buffer where input logic level equals the output logic level, while providing buffering and drive to the output. The SN74LV4T125 device will also translate voltages up or down while performing this function.

Table 1. Function Table
(Each Buffer)

INPUTS OUTPUT
Y
OE A
L H H
L L L
H X Z

Table 2. Supply VCC = 3.3 V

INPUT b
(Lower Level Input)
OUTPUT
(VCC CMOS)
A B Y
VIH(min) = 1.35 V VOH(min) = 2.9 V
VIL(max) = 0.8 V VOL(max) = 0.2 V