SCLS413K April   1998  – December 2022 SN74LV594A

PRODMIX  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics: VCC = 2.5 V ± 0.2 V
    7. 6.7  Switching Characteristics: VCC = 3.3 V ± 0.3 V
    8. 6.8  Switching Characteristics: VCC = 5 V ± 0.5 V
    9. 6.9  Timing Requirements: VCC = 2.5 V ± 0.2 V
    10. 6.10 Timing Requirements: VCC = 3.3 V ± 0.3 V
    11. 6.11 Timing Requirements: VCC = 5 V ± 0.5 V
    12. 6.12 Noise Characteristics
    13. 6.13 Operating Characteristics
    14. 6.14 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • BQB|16
  • DB|16
  • PW|16
  • D|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • VCC operation of 2 V to 5.5 V
  • Maximum tpd of 6.5 ns at 5 V
  • Typical VOLP (output ground bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
  • Support mixed-mode voltage operation on all ports
  • 8-bit serial-in, parallel-out shift registers with storage
  • Independent direct overriding clears on shift and storage registers
  • Independent clocks for shift and storage registers
  • Latch-up performance exceeds 100 mA per JESD 78, Class II