SCAS279R January   1993  – February 2016 SN54LVC00A , SN74LVC00A

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Simplified Schematic
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 ESD Ratings
    2. 6.2 Thermal Information
    3. 6.3 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
  • RGY|14
  • DB|14
  • PW|14
  • NS|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Detailed Description

7.1 Overview

The maximum sink and source current is 24mA.

Inputs can be driven from 1.8-V, 2.5-V, 3.3-V (LVTTL), or 5-V (CMOS) devices. This feature allows the use of this device as translators in a mixed-system environment.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

7.2 Functional Block Diagram

Logic Diagram, Each Gate (Positive Logic)

SN54LVC00A SN74LVC00A ld_cas279.gif

7.3 Feature Description

  • Wide operating voltage range
    • Operates from 1.65 V to 3.6 V
  • Allows up or down voltage translation
    • Inputs and outputs accept voltages to 5.5 V
  • Ioff feature
    • Allows voltages on the inputs and outputs when VCC is 0 V

7.4 Device Functional Modes

Table 1. Function Table
(Each Gate)

INPUTS OUTPUT
Y
A B
H H L
L X H
X L H