8.1 Overview

The SN74LVC1G123 device is a single retriggerable monostable multivibrator designed for 1.65-V to 5.5-V V_CC operation.

This monostable multivibrator features output pulse-duration control by three methods. In the first method, the A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.

The output pulse duration is programmed by selecting external resistance and capacitance values. The external timing capacitor must be connected between C_ext and R_ext/C_ext (positive) and an external resistor connected between R_ext/C_ext and V_CC. To obtain variable pulse durations, connect an external variable resistance between R_ext/C_ext and V_CC. The output pulse duration also can be reduced by taking CLR low.

Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. The A and B inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition rates with jitter-free triggering at the outputs.

Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A) or high-level-active (B) input. Pulse duration can be reduced by taking CLR low. CLR can be used to override A or B inputs. The input/output timing diagram illustrates pulse control by retriggering the inputs and early clearing.

The SN74LVC1G123 device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

8.2 Functional Block Diagram

8.3 Feature Description

This part is available in the Texas Instruments NanoFree™ package. It supports 5-V V_CC operation and accepts inputs up to 5.5 V. The max t_pd is 8 ns at 3.3 V. It supports mixed-mode voltage operation on all ports.

Down translation can be achieved to V_CC from up to 5.5 V.

Schmitt-trigger circuitry on A and B inputs allows for slow input transition rates. The device can be edge triggered from active-high or active-low gated logic inputs. It can support up to 100% duty cycle from retriggering.

Clear can be used to terminate the output pulse early.

Glitch-free power-up reset is on all outputs.

I_off supports live insertion, partial-power-down mode, and back-drive protection.

Latch-up performance exceeds 100 mA per JESD 78, Class II.

8.4 Device Functional Modes

Table 1 lists the functional modes for the SN74LVC1G123.

Table 1. Function Table

INPUTS			OUTPUTS Q
CLR	A	B
L	X	X	L
X	H	X	L(1)
X	X	L	L(1)
H	L	↑
H	↓	H
↑	L	H

(1) These outputs are based on the assumption that the indicated steady-state conditions at the A and B inputs have been set up long enough to complete any pulse started before the setup.