SCES515M December   2003  – November 2022 SN74LVC1T45

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics (VCCA = 1.8 V ± 0.15 V)
    7. 6.7  Switching Characteristics (VCCA = 2.5 V ± 0.2 V)
    8. 6.8  Switching Characteristics (VCCA = 3.3 V ± 0.3 V)
    9. 6.9  Switching Characteristics (VCCA = 5 V ±0.5 V)
    10. 6.10 Operating Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.5-V Power-Supply Range
      2. 8.3.2 Support High Speed Translation
      3. 8.3.3 Ioff Supports Partial Power-Down Mode Operation
      4. 8.3.4 Balanced High-Drive CMOS Push-Pull Outputs
      5. 8.3.5 Vcc Isolation
    4. 8.4 Device Functional Modes
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Unidirectional Logic Level-Shifting Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Bidirectional Logic Level-Shifting Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Enable Times
        3. 9.2.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Revision History

Changes from Revision L (February 2017) to Revision M (November 2022)

  • Updated the numbering format for tables, figures, and cross-references throughout the documentGo
  • Updated the thermals in the Thermal Information sectionGo
  • Updated the Switching Characterisitcs sections: extended some minimum specifications for lower delays Go
  • Updated the Ioff Supports Partial Power-Down Mode Operation sectionGo
  • Added the Balanced High-Drive CMOS Push-Pull Outputs and VCC Isolation sectionsGo
  • Updated the Power Supply Recommendations sectionGo

Changes from Revision K (December 2014) to Revision L (February 2017)

  • Added DPK (USON) package informationGo
  • Added Documentation Support section, Receiving Notification of Documentation Updates section, and Community Resources sectionGo
  • Added Junction temperature, TJ in Absolute Maximum Ratings Go

Changes from Revision J (December 2013) to Revision K (December 2014)

  • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go

Changes from Revision I (December 2011) to Revision J (December 2013)

  • Updated document to new TI data sheet format - no specification changesGo
  • Removed ordering information.Go
  • Added ESD warning.Go