SCES204Q April 1999 – March 2017 SN74LVC2G125
Refer to the PDF data sheet for device specific package drawings
The SN74LVC2G125 device is a dual bus buffer gate, designed for 1.65-V to 5.5-V VCC operation. This device features dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is high.
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To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
|PART NUMBER||PACKAGE||BODY SIZE|
|SN74LVC2G125DCTR||SM8 (8)||2.95 mm × 2.80 mm|
|SN74LVC2G125DCUR||VSSOP (8)||2.30 mm × 2.00 mm|
|SN74LVC2G125YZPR||DSBGA (8)||1.91 mm × 0.91 mm|