SCES920B September   2020  – March 2023 SN74LXC8T245-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics, VCCA = 1.2 ± 0.1 V
    7. 6.7  Switching Characteristics, VCCA = 1.5 ± 0.1 V
    8. 6.8  Switching Characteristics, VCCA = 1.8 ± 0.15 V
    9. 6.9  Switching Characteristics, VCCA = 2.5 ± 0.2 V
    10. 6.10 Switching Characteristics, VCCA = 3.3 ± 0.3 V
    11. 6.11 Switching Characteristics, VCCA = 5.0 ± 0.5 V
    12. 6.12 Switching Characteristics: Tsk, TMAX
    13. 6.13 Operating Characteristics
    14. 6.14 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Load Circuit and Voltage Waveforms
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 CMOS Schmitt-Trigger Inputs with Integrated Pulldowns
        1. 8.3.1.1 I/Os with Integrated Dynamic Pull-Down Resistors
        2. 8.3.1.2 Control Inputs with Integrated Static Pull-Down Resistors
      2. 8.3.2 Balanced High-Drive CMOS Push-Pull Outputs
      3. 8.3.3 Partial Power Down (Ioff)
      4. 8.3.4 VCC Isolation and VCC Disconnect (Ioff-float)
      5. 8.3.5 Over-Voltage Tolerant Inputs
      6. 8.3.6 Glitch-Free Power Supply Sequencing
      7. 8.3.7 Negative Clamping Diodes
      8. 8.3.8 Fully Configurable Dual-Rail Design
      9. 8.3.9 Supports High-Speed Translation
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The SN74LXC8T245-Q1 is an 8-bit, dual-supply noninverting bidirectional voltage level translation device. Ax pins and control pins (DIR and OE) are referenced to VCCA logic levels, and Bx pins are referenced to VCCB logic levels. The A port is able to accept I/O voltages ranging from 1.1 V to 5.5 V, while the B port can accept I/O voltages from 1.1 V to 5.5 V. A high on DIR allows data transmission from A to B and a low on DIR allows data transmission from B to A when OE is set to low. When OE is set to high, both Ax and Bx pins are in the high-impedance state. See Device Functional Modes for a summary of the operation of the control logic.

Package Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
SN74LXC8T245-Q1 PW (TSSOP, 24) 7.80 mm × 6.40 mm
RHL (VQFN, 24) 5.50 mm × 3.50 mm
DGS (VSSOP, 24) 6.10 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-FAB7F568-51F0-4ECE-82A2-8233B382F0F5-low.gif Functional Block Diagram