SLLS505P February   2002  – February 2022 SN65HVD10 , SN65HVD11 , SN65HVD12 , SN75HVD12

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Driver Electrical Characteristics
    6. 7.6  Receiver Electrical Characteristics
    7. 7.7  Power Dissipation Characteristics
    8. 7.8  Driver Switching Characteristics
    9. 7.9  Receiver Switching Characteristics
    10. 7.10 Dissipation Ratings
    11. 7.11 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
      1. 9.4.1 Low-Power Standby Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Data Rate and Bus Length
        2. 10.2.1.2 Stub Length
        3. 10.2.1.3 Bus Loading
        4. 10.2.1.4 Receiver Fail-safe
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Considerations
      1. 12.3.1 Thermal Characteristics of IC Packages
  13. 13Device and Documentation Support
    1. 13.1 Device Support
    2. 13.2 Related Links
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The SN65HVD10, SN75HVD10, SN65HVD11, SN75HVD11, SN65HVD12, and SN75HVD12 bus transceivers all combine a 3-state differential line driver, as well as a differential input line receiver that operates with a single 3.3-V power supply. They are designed for balanced transmission lines and meet or exceed ANSI standard TIA/EIA-485-A and ISO 8482:1993. These differential bus transceivers are monolithic integrated circuits, designed for bidirectional data communication on multipoint bus-transmission lines. The drivers and receivers have active-high and active-low enables, that can be externally connected together to function as direction control. Very low device standby supply current, can be achieved by disabling the driver and the receiver.

The driver differential outputs and receiver differential inputs connect internally to form a differential input/output (I/O) bus port, that is designed to offer minimum loading to the bus whenever the driver is disabled or VCC = 0. These parts feature wide positive and negative common-mode voltage ranges, making them suitable for party-line applications.

Device Information
PART NUMBERPACKAGE(1)BODY SIZE (NOM)
SN65HVD10SOIC (8)4.90 mm × 3.91 mm
SN65HVD11
SN65HVD12
SN75HVD10PDIP (8)9.81 mm × 6.35 mm
SN75HVD11
SN75HVD12
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-F5604E8B-4036-4B98-9093-ED1DCDA5FF68-low.gifTypical Application Diagram