SNLS693B December   2021  – December 2023 SN75LVPE5412

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 DC Electrical Characteristics
    6. 5.6 High Speed Electrical Characteristics
    7. 5.7 SMBUS/I2C Timing Characteristics
    8. 5.8 Typical Characteristics
    9. 5.9 Typical Jitter Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Five-Level Control Inputs
      2. 6.3.2 Linear Equalization
      3. 6.3.3 Flat Gain
      4. 6.3.4 Receiver Detect State Machine
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active PCIe Mode
      2. 6.4.2 Active Buffer Mode
      3. 6.4.3 Standby Mode
    5. 6.5 Programming
      1. 6.5.1 Pin Mode
      2. 6.5.2 SMBUS/I2C Register Control Interface
        1. 6.5.2.1 Shared Registers
        2. 6.5.2.2 Channel Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 PCIe x8 Lane Switching
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
      2. 7.2.2 Protocol Agnostic Linear Redriver for High Speed Interfaces
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RUA|42
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2.2 Protocol Agnostic Linear Redriver for High Speed Interfaces

The SN75LVPE5412 can be used as a four channel protocol agnostic linear redriver demultiplexer (demux) for data rates up to 32Gbps. To use the device in a non-PCIe application, the RX_DET pin must be pin-strapped to GND with 1kΩ resistor (L0).

This section explains how the SN75LVPE5412 can be used in DisplayPort (DP) application. The device is a linear redriver which is agnostic to DP link training. The DP link training negotiation between a display source and sink stays effective through the device. The redriver becomes part of the electrical channel along with passive traces, cables, and so forth, resulting in optimum source and sink parameters for best electrical link.

Figure 7-2 shows a simplified schematic for DisplayPort demultiplexing application using SN75LVPE5412. Auxiliary and Hot plug detect (HPD) are demuxed outside of the device. If system use case requires implementing DP power states, then the device must be controlled by the I2C.

GUID-20220620-SS0I-DVTX-PLMV-4KCJHQBNSC9T-low.svg Figure 7-2 Simplified Schematic for DisplayPort Demultiplexer Application

The inverted DisplayPort HPD signal can be used to put the device into standby mode by using its PD pin. Note: in a DisplayPort link a sink can use HPD line to create an interrupt for its link partner source. If HPD signal is used for power management, then an RC filter must be installed to filter out HPD interrupt signals.

The SN75LVPE5412 can similarly be used for other AC-coupled high speed interfaces. Care must be taken to understand the specifications of the interface to ensure feasibility.