SNLS692B December   2021  – December 2023 SN75LVPE5421

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 DC Electrical Characteristics
    6. 5.6 High Speed Electrical Characteristics
    7. 5.7 SMBUS/I2C Timing Characteristics
    8. 5.8 Typical Characteristics
    9. 5.9 Typical Jitter Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Five-Level Control Inputs
      2. 6.3.2 Linear Equalization
      3. 6.3.3 Flat Gain
      4. 6.3.4 Receiver Detect State Machine
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active PCIe Mode
      2. 6.4.2 Active Buffer Mode
      3. 6.4.3 Standby Mode
    5. 6.5 Programming
      1. 6.5.1 Pin Mode
      2. 6.5.2 SMBUS/I2C Register Control Interface
        1. 6.5.2.1 Shared Registers
        2. 6.5.2.2 Channel Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 PCIe x8 Lane Switching
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
      2. 7.2.2 Protocol Agnostic Linear Redriver for High Speed Interfaces
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RUA|42
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.4 Receiver Detect State Machine

The SN75LVPE5421 deploys an RX detect state machine that governs the RX detection cycle as defined in the PCI express specifications. At device power up or through manually triggered event using PD or SEL pin or writing to the relevant I2C/SMBus register, the redriver determines whether or not a valid PCI express termination is present at the far end of the link. The RX_DET pin of SN75LVPE5421 provides additional flexibility for system designers to appropriately set the device in desired mode according to Table 6-4. For the PCIe application the RX_DET pin can be left floating for default settings.

Note: power up ramp or PD/SEL event triggers RX detect for all four channels. In applications where SN75LVPE5421 channels are used for multiple PCIe links, the RX detect function can be performed for individual channels through writing in appropriate I2C/SMBus registers.

Table 6-4 Receiver Detect State Machine Settings
PDRX_DETRX Common-mode ImpedanceCOMMENTS
LL0Always 50 ΩPCI Express RX detection state machine is disabled. Recommended for non PCIe interface use case where the SN75LVPE5421 is used as buffer with equalization.
L L1 Pre Detect: Hi-Z
Post Detect: 50 Ω.		 Outputs polls until 3 consecutive valid detections
L L2 Pre Detect: Hi-Z
Post Detect: 50 Ω.		 Outputs polls until 2 consecutive valid detections
L L3 Pre Detect: Hi-Z
Post Detect: 50 Ω.		 Reserved
LL4 (Float)Pre Detect: Hi-Z
Post Detect: 50 Ω.		TX polls every ≅150 µs until valid termination is detected. RX CM impedance held at Hi-Z until detection Reset by asserting PD high for 200 µs then low. Recommended default setting for PCIe.
HXHi-ZReset Channels and set their RX impedance to Hi-Z