SLASF38A December   2023  â€“ March 2025 TAD5212-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements: I2C Interface
    7. 5.7  Switching Characteristics: I2C Interface
    8. 5.8  Timing Requirements: SPI
    9. 5.9  Switching Characteristics: SPI
    10. 5.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 5.11 Switching Characteristics: TDM, I2S or LJ Interface
    12. 5.12 Timing Requirements: PDM Digital Microphone Interface
    13. 5.13 Switching Characteristics: PDM Digial Microphone Interface
    14. 5.14 Timing Diagrams
    15. 5.15 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Serial Interfaces
        1. 6.3.1.1 Control Serial Interfaces
        2. 6.3.1.2 Audio Serial Interfaces
          1. 6.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 6.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 6.3.1.2.3 Left-Justified (LJ) Interface
        3. 6.3.1.3 Using Multiple Devices With Shared Buses
      2. 6.3.2 Phase-Locked Loop (PLL) and Clock Generation
      3. 6.3.3 Output Channel Configurations
      4. 6.3.4 Reference Voltage
      5. 6.3.5 Programmable Microphone Bias
      6. 6.3.6 Digital PDM Microphone Record Channel
      7. 6.3.7 Signal-Chain Processing
        1. 6.3.7.1 DAC Signal-Chain
          1. 6.3.7.1.1 Programmable Channel Gain and Digital Volume Control
          2. 6.3.7.1.2 Programmable Channel Gain Calibration
          3. 6.3.7.1.3 Programmable Digital High-Pass Filter
          4. 6.3.7.1.4 Programmable Digital Biquad Filters
          5. 6.3.7.1.5 Configurable Digital Interpolation Filters
            1. 6.3.7.1.5.1 Linear-phase filters
              1. 6.3.7.1.5.1.1 Sampling Rate: 8kHz or 7.35kHz
              2. 6.3.7.1.5.1.2 Sampling Rate: 16kHz or 14.7kHz
              3. 6.3.7.1.5.1.3 Sampling Rate: 24kHz or 22.05kHz
              4. 6.3.7.1.5.1.4 Sampling Rate: 32kHz or 29.4kHz
              5. 6.3.7.1.5.1.5 Sampling Rate: 48kHz or 44.1kHz
              6. 6.3.7.1.5.1.6 Sampling Rate: 96kHz or 88.2kHz
              7. 6.3.7.1.5.1.7 Sampling Rate: 192kHz or 176.4kHz
              8. 6.3.7.1.5.1.8 Sampling Rate: 384kHz or 352.8kHz
              9. 6.3.7.1.5.1.9 Sampling Rate 768kHz or 705.6kHz
            2. 6.3.7.1.5.2 Low-latency Filters
              1. 6.3.7.1.5.2.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.1.5.2.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.1.5.2.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.1.5.2.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.1.5.2.5 Sampling Rate: 192kHz or 176.4kHz
            3. 6.3.7.1.5.3 Ultra-Low-Latency Filters
              1. 6.3.7.1.5.3.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.1.5.3.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.1.5.3.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.1.5.3.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.1.5.3.5 Sampling Rate 192kHz or 176.4kHz
          6. 6.3.7.1.6 Programmable Digital Mixer
        2. 6.3.7.2 PDM Recording Signal-Chain
          1. 6.3.7.2.1 Programmable Channel Gain and Digital Volume Control
          2. 6.3.7.2.2 Programmable Channel Gain Calibration
          3. 6.3.7.2.3 Programmable Channel Phase Calibration
          4. 6.3.7.2.4 Programmable Digital High-Pass Filter
          5. 6.3.7.2.5 Programmable Digital Biquad Filters
          6. 6.3.7.2.6 Configurable Digital Decimation Filters
            1. 6.3.7.2.6.1 Linear-phase filters
              1. 6.3.7.2.6.1.1 Sampling Rate: 8kHz or 7.35kHz
              2. 6.3.7.2.6.1.2 Sampling Rate: 16kHz or 14.7kHz
              3. 6.3.7.2.6.1.3 Sampling Rate: 24kHz or 22.05kHz
              4. 6.3.7.2.6.1.4 Sampling Rate: 32kHz or 29.4kHz
              5. 6.3.7.2.6.1.5 Sampling Rate: 48kHz or 44.1kHz
              6. 6.3.7.2.6.1.6 Sampling Rate: 96kHz or 88.2kHz
              7. 6.3.7.2.6.1.7 Sampling Rate: 192kHz or 176.4kHz
            2. 6.3.7.2.6.2 Low-latency Filters
              1. 6.3.7.2.6.2.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.2.6.2.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.2.6.2.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.2.6.2.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.2.6.2.5 Sampling Rate: 192kHz or 176.4kHz
            3. 6.3.7.2.6.3 Ultra Low-latency Filters
              1. 6.3.7.2.6.3.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.2.6.3.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.2.6.3.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.2.6.3.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.2.6.3.5 Sampling Rate: 192kHz or 176.4kHz
          7. 6.3.7.2.7 Automatic Gain Controller (AGC)
          8. 6.3.7.2.8 Voice Activity Detection (VAD)
          9. 6.3.7.2.9 Ultrasonic Activity Detection (UAD)
      8. 6.3.8 Interrupts, Status, and Digital I/O Pin Multiplexing
      9. 6.3.9 Power Tune Mode
    4. 6.4 Device Functional Modes
      1. 6.4.1 Sleep Mode or Software Shutdown
      2. 6.4.2 Active Mode
      3. 6.4.3 Software Reset
    5. 6.5 Programming
      1. 6.5.1 Control Serial Interfaces
        1. 6.5.1.1 I2C Control Interface
          1. 6.5.1.1.1 General I2C Operation
          2. 6.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
            1. 6.5.1.1.2.1 I2C Single-Byte Write
            2. 6.5.1.1.2.2 I2C Multiple-Byte Write
            3. 6.5.1.1.2.3 I2C Single-Byte Read
            4. 6.5.1.1.2.4 I2C Multiple-Byte Read
        2. 6.5.1.2 SPI Control Interface
  8. Register Maps
    1. 7.1 Device Configuration Registers
      1. 7.1.1 TAD5212_B0_P0 Registers
      2. 7.1.2 TAD5212_B0_P1 Registers
      3. 7.1.3 TAD5212_B0_P3 Registers
    2. 7.2 Programmable Coefficient Registers
      1. 7.2.1  Programmable Coefficient Registers: Page 8
      2. 7.2.2  Programmable Coefficient Registers: Page 9
      3. 7.2.3  Programmable Coefficient Registers: Page 10
      4. 7.2.4  Programmable Coefficient Registers: Page 11
      5. 7.2.5  Programmable Coefficient Registers: Page 15
      6. 7.2.6  Programmable Coefficient Registers: Page 16
      7. 7.2.7  Programmable Coefficient Registers: Page 17
      8. 7.2.8  Programmable Coefficient Registers: Page 18
      9. 7.2.9  Programmable Coefficient Registers: Page 19
      10. 7.2.10 Programmable Coefficient Registers: Page 25
      11. 7.2.11 Programmable Coefficient Registers: Page 26
      12. 7.2.12 Programmable Coefficient Registers: Page 27
      13. 7.2.13 Programmable Coefficient Registers: Page 28
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Performance Plots
      5. 8.2.5 Example Device Register Configuration Script for EVM Setup
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 AVDD_MODE for 1.8V Operation
      2. 8.3.2 IOVDD_IO_MODE for 1.8V and 1.2V Operation
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
Programmable Digital Biquad Filters

The device supports up to 12 programmable digital biquad filters available for record signal chain limited to 3/channel. These highly efficient filters achieve the desired frequency response. The TAD5212-Q1 also supports on-the-fly programmable Biquad filters for two-channel record use cases. In digital signal processing, a digital biquad filter is a second-order, recursive linear filter with two poles and two zeros. Equation 4 gives the transfer function of each biquad filter:

Equation 4. TAD5212-Q1

The frequency response for the biquad filter section with default coefficients is flat at a gain of 0dB (all-pass filter). The host device can override the frequency response by programming the biquad coefficients to achieve the desired frequency response for low-pass, high-pass, or any other desired frequency shaping. The programmable coefficients for the biquads are located in the B0_P8 and B0_P9. If biquad filtering is required, then the host device must write these coefficient values before powering up any record channels for recording. In two-channel use case, the TAD5212-Q1 also supports on-the-fly programmable filters. In this case, the device uses two banks of filters for one channel with a switch bit to perform the switch from one filter bank to the other. As described in Table 6-46, these biquad filters can be allocated for each output channel based on the ADC_DSP_BQ_CFG[1:0] register setting of P0_R114_D[3:2]. By setting ADC_DSP_BQ_CFG[1:0] to 2'b00, the biquad filtering for all record channels is disabled and the host device can choose this setting if no additional filtering is required for the system application. See the TAC5x1x and TAC5x1x-Q1 Programmable Biquad Filters - Configuration and Applications application report for further details.

Table 6-46 Biquad Filter Allocation to the Record Output Channel
PROGRAMMABLE BIQUAD FILTERRECORD OUTPUT CHANNEL ALLOCATION USING P0_R114_D[3:2] REGISTER SETTING
ADC_DSP_BQ_CFG[1:0] = 2'b01
(1 Biquad per Channel)
ADC_DSP_BQ_CFG[1:0] = 2'b10 (Default)
(2 Biquads per Channel)
ADC_DSP_BQ_CFG[1:0] = 2'b11
(3 Biquads per Channel)
Biquad filter 1Allocated to output channel 1Allocated to output channel 1Allocated to output channel 1
Biquad filter 2Allocated to output channel 2Allocated to output channel 2Allocated to output channel 2
Biquad filter 3Allocated to output channel 3Allocated to output channel 3Allocated to output channel 3
Biquad filter 4Allocated to output channel 4Allocated to output channel 4Allocated to output channel 4
Biquad filter 5Not usedAllocated to output channel 1Allocated to output channel 1
Biquad filter 6Not usedAllocated to output channel 2Allocated to output channel 2
Biquad filter 7Not usedAllocated to output channel 3Allocated to output channel 3
Biquad filter 8Not usedAllocated to output channel 4Allocated to output channel 4
Biquad filter 9Not usedNot usedAllocated to output channel 1
Biquad filter 10Not usedNot usedAllocated to output channel 2
Biquad filter 11Not usedNot usedAllocated to output channel 3
Biquad filter 12Not usedNot usedAllocated to output channel 4

Table 6-47 shows the biquad filter coefficients mapping to the register space.

Table 6-47 Biquad Filter Coefficients Register Mapping
PROGRAMMABLE BIQUAD FILTERBIQUAD FILTER COEFFICIENTS REGISTER MAPPINGPROGRAMMABLE BIQUAD FILTERBIQUAD FILTER COEFFICIENTS REGISTER MAPPING
Biquad filter 1P8_R8-R27Biquad filter 7P9_R8-R27
Biquad filter 2P8_R28-R47Biquad filter 8P9_R28-R47
Biquad filter 3P8_R48-R67Biquad filter 9P9_R48-R67
Biquad filter 4P8_R68-R87Biquad filter 10P9_R68-R87
Biquad filter 5P8_R88-R107Biquad filter 11P9_R88-R107
Biquad filter 6P8_R108-R127Biquad filter 12P9_R108-R127