SLASF38A December   2023  – March 2025 TAD5212-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements: I2C Interface
    7. 5.7  Switching Characteristics: I2C Interface
    8. 5.8  Timing Requirements: SPI
    9. 5.9  Switching Characteristics: SPI
    10. 5.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 5.11 Switching Characteristics: TDM, I2S or LJ Interface
    12. 5.12 Timing Requirements: PDM Digital Microphone Interface
    13. 5.13 Switching Characteristics: PDM Digial Microphone Interface
    14. 5.14 Timing Diagrams
    15. 5.15 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Serial Interfaces
        1. 6.3.1.1 Control Serial Interfaces
        2. 6.3.1.2 Audio Serial Interfaces
          1. 6.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 6.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 6.3.1.2.3 Left-Justified (LJ) Interface
        3. 6.3.1.3 Using Multiple Devices With Shared Buses
      2. 6.3.2 Phase-Locked Loop (PLL) and Clock Generation
      3. 6.3.3 Output Channel Configurations
      4. 6.3.4 Reference Voltage
      5. 6.3.5 Programmable Microphone Bias
      6. 6.3.6 Digital PDM Microphone Record Channel
      7. 6.3.7 Signal-Chain Processing
        1. 6.3.7.1 DAC Signal-Chain
          1. 6.3.7.1.1 Programmable Channel Gain and Digital Volume Control
          2. 6.3.7.1.2 Programmable Channel Gain Calibration
          3. 6.3.7.1.3 Programmable Digital High-Pass Filter
          4. 6.3.7.1.4 Programmable Digital Biquad Filters
          5. 6.3.7.1.5 Configurable Digital Interpolation Filters
            1. 6.3.7.1.5.1 Linear-phase filters
              1. 6.3.7.1.5.1.1 Sampling Rate: 8kHz or 7.35kHz
              2. 6.3.7.1.5.1.2 Sampling Rate: 16kHz or 14.7kHz
              3. 6.3.7.1.5.1.3 Sampling Rate: 24kHz or 22.05kHz
              4. 6.3.7.1.5.1.4 Sampling Rate: 32kHz or 29.4kHz
              5. 6.3.7.1.5.1.5 Sampling Rate: 48kHz or 44.1kHz
              6. 6.3.7.1.5.1.6 Sampling Rate: 96kHz or 88.2kHz
              7. 6.3.7.1.5.1.7 Sampling Rate: 192kHz or 176.4kHz
              8. 6.3.7.1.5.1.8 Sampling Rate: 384kHz or 352.8kHz
              9. 6.3.7.1.5.1.9 Sampling Rate 768kHz or 705.6kHz
            2. 6.3.7.1.5.2 Low-latency Filters
              1. 6.3.7.1.5.2.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.1.5.2.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.1.5.2.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.1.5.2.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.1.5.2.5 Sampling Rate: 192kHz or 176.4kHz
            3. 6.3.7.1.5.3 Ultra-Low-Latency Filters
              1. 6.3.7.1.5.3.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.1.5.3.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.1.5.3.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.1.5.3.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.1.5.3.5 Sampling Rate 192kHz or 176.4kHz
          6. 6.3.7.1.6 Programmable Digital Mixer
        2. 6.3.7.2 PDM Recording Signal-Chain
          1. 6.3.7.2.1 Programmable Channel Gain and Digital Volume Control
          2. 6.3.7.2.2 Programmable Channel Gain Calibration
          3. 6.3.7.2.3 Programmable Channel Phase Calibration
          4. 6.3.7.2.4 Programmable Digital High-Pass Filter
          5. 6.3.7.2.5 Programmable Digital Biquad Filters
          6. 6.3.7.2.6 Configurable Digital Decimation Filters
            1. 6.3.7.2.6.1 Linear-phase filters
              1. 6.3.7.2.6.1.1 Sampling Rate: 8kHz or 7.35kHz
              2. 6.3.7.2.6.1.2 Sampling Rate: 16kHz or 14.7kHz
              3. 6.3.7.2.6.1.3 Sampling Rate: 24kHz or 22.05kHz
              4. 6.3.7.2.6.1.4 Sampling Rate: 32kHz or 29.4kHz
              5. 6.3.7.2.6.1.5 Sampling Rate: 48kHz or 44.1kHz
              6. 6.3.7.2.6.1.6 Sampling Rate: 96kHz or 88.2kHz
              7. 6.3.7.2.6.1.7 Sampling Rate: 192kHz or 176.4kHz
            2. 6.3.7.2.6.2 Low-latency Filters
              1. 6.3.7.2.6.2.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.2.6.2.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.2.6.2.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.2.6.2.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.2.6.2.5 Sampling Rate: 192kHz or 176.4kHz
            3. 6.3.7.2.6.3 Ultra Low-latency Filters
              1. 6.3.7.2.6.3.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.2.6.3.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.2.6.3.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.2.6.3.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.2.6.3.5 Sampling Rate: 192kHz or 176.4kHz
          7. 6.3.7.2.7 Automatic Gain Controller (AGC)
          8. 6.3.7.2.8 Voice Activity Detection (VAD)
          9. 6.3.7.2.9 Ultrasonic Activity Detection (UAD)
      8. 6.3.8 Interrupts, Status, and Digital I/O Pin Multiplexing
      9. 6.3.9 Power Tune Mode
    4. 6.4 Device Functional Modes
      1. 6.4.1 Sleep Mode or Software Shutdown
      2. 6.4.2 Active Mode
      3. 6.4.3 Software Reset
    5. 6.5 Programming
      1. 6.5.1 Control Serial Interfaces
        1. 6.5.1.1 I2C Control Interface
          1. 6.5.1.1.1 General I2C Operation
          2. 6.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
            1. 6.5.1.1.2.1 I2C Single-Byte Write
            2. 6.5.1.1.2.2 I2C Multiple-Byte Write
            3. 6.5.1.1.2.3 I2C Single-Byte Read
            4. 6.5.1.1.2.4 I2C Multiple-Byte Read
        2. 6.5.1.2 SPI Control Interface
  8. 7 Register Maps
    1. 7.1 Device Configuration Registers
      1. 7.1.1 TAD5212_B0_P0 Registers
      2. 7.1.2 TAD5212_B0_P1 Registers
      3. 7.1.3 TAD5212_B0_P3 Registers
    2. 7.2 Programmable Coefficient Registers
      1. 7.2.1  Programmable Coefficient Registers: Page 8
      2. 7.2.2  Programmable Coefficient Registers: Page 9
      3. 7.2.3  Programmable Coefficient Registers: Page 10
      4. 7.2.4  Programmable Coefficient Registers: Page 11
      5. 7.2.5  Programmable Coefficient Registers: Page 15
      6. 7.2.6  Programmable Coefficient Registers: Page 16
      7. 7.2.7  Programmable Coefficient Registers: Page 17
      8. 7.2.8  Programmable Coefficient Registers: Page 18
      9. 7.2.9  Programmable Coefficient Registers: Page 19
      10. 7.2.10 Programmable Coefficient Registers: Page 25
      11. 7.2.11 Programmable Coefficient Registers: Page 26
      12. 7.2.12 Programmable Coefficient Registers: Page 27
      13. 7.2.13 Programmable Coefficient Registers: Page 28
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Performance Plots
      5. 8.2.5 Example Device Register Configuration Script for EVM Setup
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 AVDD_MODE for 1.8V Operation
      2. 8.3.2 IOVDD_IO_MODE for 1.8V and 1.2V Operation
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

At TA = 25°C, AVDD = 3.3V, IOVDD = 3.3V, fIN = 1kHz sinusoidal signal, fS = 48kHz, 32-bit audio data, BCLK = 256 × fS, TDM target mode, PLL on, channel gain = 0dB, linear phase interpolation filters, 1200Ω/600Ω line-out load in differential/single-ended configuration or 32Ω/16Ω receiver/headphone load as applicable, MICBIAS programmed to VREF, and other default configurations; measured filter free with an Audio Precision with a 20Hz to 20kHz un-weighted bandwidth, unless otherwise noted
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
DAC Performance for Line Output/Head Phone Playback
Full Scale Output Voltage Differential output between OUTxP and OUTxM, AVDD = 3.3V 2 VRMS
Differential output between OUTxP and OUTxM, AVDD = 1.8V 1
Single-ended output, AVDD = 3.3V 1
Single-ended output, AVDD = 1.8V 0.5
Pseudo-differential output between OUTxP and OUTxM, AVDD = 3.3V 1
Pseudo-differential output between OUTxP and OUTxM, AVDD = 1.8V 0.5
SNR Signal-to-noise ratio, A-weighted(1)(2) Differential output, 0dBFS signal, AVDD=3.3V 120 dB
Single-ended output, 0dBFS signal, AVDD=3.3V 111
Pseudo-differential output, 0dBFS signal, AVDD=3.3V 112
Differential output, 0dBFS signal, AVDD=1.8V 115
Single-ended output, 0dBFS signal, AVDD=1.8V 105
Pseudo-differential output, 0dBFS signal, AVDD=1.8V 106
Differential output, 0dBFS signal, AVDD=3.3V, Power Tune Mode(3) 117
Single-ended output, 0dBFS signal, AVDD=3.3V, Power Tune Mode(3) 104
Pseudo-differential output, 0dBFS signal, AVDD=3.3V, Power Tune Mode(3) 109
Differential output, 0dBFS signal, AVDD=1.8V, Power Tune Mode(3) 112
Single-ended output, 0dBFS signal, AVDD=1.8V, Power Tune Mode(3) 100
Pseudo-differential output, 0dBFS Signal, AVDD=1.8V, Power Tune Mode(3) 104
SNR Signal-to-noise ratio, A-weighted(1)(2) Differential-output, Receiver load, 0dBFS signal, AVDD=3.3V 118 dB
Single-ended output, Headphone load, 0dBFS signal, AVDD=3.3V 110
Pseudo-differential output, Receiver load, 0dBFS signal, AVDD=3.3V 112
Differential-output, Receiver load, 0dBFS signal, AVDD=1.8V 114
Single-ended output, Headphone load, 0dBFS signal, AVDD=1.8V 105
Pseudo-differential output, Receiver load, 0dBFS signal, AVDD=1.8V 106
DR Dynamic range, A-weighted(2) Differential output, -60dBFS signal, AVDD=3.3V 120 dB
Single-ended output, -60dBFS signal, AVDD=3.3V 111
Pseudo-differential output, -60dBFS signal, AVDD=3.3V 112
Differential output, -60dBFS signal, AVDD=1.8V 115
Single-ended output, -60dBFS Signal, AVDD=1.8V 105
Pseudo-differential output, -60dBFS signal, AVDD=1.8V 107
Differential output, -60dBFS signal, AVDD=3.3V, Power Tune Mode(3) 115
Single-ended output, -60dBFS signal, AVDD=3.3V, Power Tune Mode(3) 104
Pseudo-differential output, -60dBFS signal, AVDD=3.3V, Power Tune Mode(3) 109
Differential output, -60dBFS signal, AVDD=1.8V, Power Tune Mode(3) 111
Single-ended output, -60dBFS signal, AVDD=1.8V, Power Tune Mode(3) 100
Pseudo-differential output, -60dBFS signal, AVDD=1.8V, Power Tune Mode 104
DR Dynamic range, A-weighted(2) Differential-output, Receiver load, -60dBFS signal, AVDD=3.3V 118 dB
Single-ended output, Headphone load, -60dBFS signal, AVDD=3.3V 111
Pseudo-differential output, Receiver load, -60dBFS signal, AVDD=3.3V 112
Differential-output, Receiver load, -60dBFS signal, AVDD=1.8V 114
Single-ended output, Headphone load, -60dBFS signal, AVDD=1.8V 105
Pseudo-differential output, Receiver load, -60dBFS signal, AVDD=1.8V 107
THD+N Total harmonic distortion(2) Differential output, –1dBFS signal, AVDD= 3.3V –104 dB
Differential output, –1dBFS signal, AVDD= 1.8V –95
Single-ended output, 0dBFS signal, Headphone load, AVDD=3.3V –94
Headphone load range Single-ended 4 16 600 Ω
Line-out load range Single-ended 600 Ω
Headphone/Line-out Cap load Single-ended 0 2 nF
Analog Bypass to Line Out/Head Phone Amplifier
Input impedance Input pins INxP or INxM, 4.4kΩ Input Impedance Mode 4.4 kΩ
Input pins INxP or INxM, 20kΩ Input Impedance Mode 20
Single Ended Full Scale Output AVDD = 3.3V 1 Vrms
Differential Full Scale Output AVDD = 3.3V 2 Vrms
AVDD = 1.8V 1 Vrms
Gain Error AC-Coupled Input, -6dBFS input ±0.1 dB
Noise, A-Weighted Idle Channel, AC Coupled Input Shorted to Ground, Differential output 3.5
 µVRMS
Noise, A-Weighted Idle Channel, AC Coupled Input Shorted to Ground, Single-ended output 19.7
 µVRMS
SNR Signal-to-noise ratio, A-weighted(1)(2) Idle Channel, AC-Coupled Input Shorted to Ground, Differential output 115
 dB
SNR Signal-to-noise ratio, A-weighted(1)(2) Idle Channel, AC-Coupled Input Shorted to Ground, Single-ended output 95
 dB
THD+N Total harmonic distortion(2) IN1 differential AC-coupled Input and -1dBFS AC signal input, 0dB channel gain –102
 dB
DAC Channel OTHER PARAMETERS
Output Offset 0 Input, Differential line-output ±0.5 mV
Output Common Mode Common Mode Level for OUTxP and OUTxM, AVDD = 1.8V (Register Configurable) 0.9 V
Common Mode Level for OUTxP and OUTxM AVDD = 3.3V (Register Configurable) 1.65
Common Mode Error DC Error in Common Mode Voltage ±20 mV
Output Signal Bandwidth Up to 192KSPS FS Rate 0.46 FS
>192KSPS 90 kHz
Input data sample rate Programmable 4 768 kHz
Input data sample word length Programmable 16 32 Bits
Digital high-pass filter cutoff frequency First-order IIR filter with programmable coefficients,
–3dB point (default setting)		 1 Hz
Interchannel isolation Differential output, –1dBFS input signal on nonmeasurement channel –134
 dB
Gain Error Differential output, –6dBFS Input signal ±0.1 dB
Interchannel gain mismatch Differential output, –6dBFS Input signal ±0.1 dB
Interchannel phase mismatch Differential output, –6dBFS Input signal ±0.01 Degrees
PSRR Power-supply rejection ratio 100mVPP, 1kHz sinusoidal signal on AVDD, differential output, 0dB channel gain 120
 dB
Mute Attenuation –130 dB
Pout Output Power Delivery Single-ended/Pseudo-differential headphone RL=16Ω, THD+N<0.1% 62.5 mW
MICROPHONE BIAS
MICBIAS noise Bandwidth = 20Hz to 20kHz, A-weighted, 1µF capacitor between MICBIAS and VSS (thermal pad) 2 µVRMS
MICBIAS voltage Bypass to AVDD AVDD V
AVDD = 1.8V 1.375 V
AVDD = 3.3V 2.75 V
DIGITAL I/O
VIL Low-level digital input logic voltage threshold All digital pins except SDA and SCL, IOVDD 1.8V or 1.2V operation –0.3 0.35 × IOVDD V
All digital pins except SDA and SCL, IOVDD 3.3V operation –0.3 0.8
VIH High-level digital input logic voltage threshold All digital pins except SDA and SCL, IOVDD 1.8V or 1.2V operation 0.65 × IOVDD IOVDD + 0.3 V
All digital pins except SDA and SCL, IOVDD 3.3V operation 2 IOVDD + 0.3
VOL Low-level digital output voltage All digital pins except SDA and SCL, IOL = –2mA, IOVDD 1.8V or 1.2V operation 0.45 V
All digital pins except SDA and SCL, IOL = –2mA, IOVDD 3.3V operation 0.4
VOH High-level digital output voltage All digital pins except SDA and SCL, IOH = 2mA, IOVDD 1.8V or 1.2V operation IOVDD – 0.45 V
All digital pins except SDA and SCL, IOH = 2mA, IOVDD 3.3V operation 2.4
VIL(I2C) Low-level digital input logic voltage threshold SDA and SCL –0.5 0.3 × IOVDD V
VIH(I2C) High-level digital input logic voltage threshold SDA and SCL 0.7 × IOVDD IOVDD + 0.5 V
VOL1(I2C) Low-level digital output voltage SDA, IOL(I2C) = –3mA, IOVDD 3.3V operation 0.4 V
VOL2(I2C) Low-level digital output voltage SDA, IOL(I2C) = –2mA, IOVDD 1.8V or 1.2V operation 0.2 x IOVDD V
IOL(I2C) Low-level digital output current SDA, VOL(I2C) = 0.4V, standard-mode or fast-mode 3 mA
SDA, VOL(I2C) = 0.4V, fast-mode plus 20
IIL Input logic-low leakage for digital inputs All digital pins, input = 0V –5 0.1 5 µA
IIH Input logic-high leakage for digital inputs All digital pins, input = IOVDD –5 0.1 5 µA
CIN Input capacitance for digital inputs All digital pins 5 pF
RPD Pulldown resistance for digital I/O pins when asserted on 20 kΩ
TYPICAL SUPPLY CURRENT CONSUMPTION
IAVDD Current consumption in sleep mode (software shutdown mode) All device external clocks stopped 9 µA
IIOVDD 1
IAVDD Current consumption with MICBIAS ON, 5mA load, no recording/playback fS = 48kHz, BCLK = 256 × fS 1.5 mA
IIOVDD 0.02
IAVDD Current consumption with DAC to Headphone 2-channel operation, MICBIAS off, PLL on fS = 16kHz, BCLK = 512 × fS 18.8 mA
IIOVDD 0.02
IAVDD Current consumption with DAC to Headphone 2-channel operation, MICBIAS off, PLL off fS = 48kHz, BCLK = 512 × fS 16 mA
IIOVDD 0.04
IAVDD Power Tune Mode(3): Current consumption with DAC to Lineout 2-channel single-ended operation, MICBIAS off, PLL off, AVDD=1.8V fS = 48kHz, BCLK = 128 × fS 5.6 mA
IAVDD Power Tune Mode(3): Current consumption with DAC to Lineout 2-channel operation, MICBIAS off, PLL on fS = 48kHz, BCLK = 512 × fS 9.2 mA
IIOVDD 0.04
(1) Ratio of output level with 1kHz full-scale sine-wave input, to the output level with no generator input signal and input shorted to ground, measured with an A-weighted filter over a 20Hz to 20kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20kHz low-pass filter and, where noted, an A-weighted filter. Failure to use such a filter can result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, can affect dynamic specification values.
(3) PWR_TUNE_CFG0 = 0xD4, PWR_TUNE_CFG1 = 0x96 and PLL_DIS = 1'b1 for Power Tune Mode