SLASFC6A August   2024  – August 2025 TAS2120

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
      1. 6.3.1 Operational Modes
        1. 6.3.1.1 Hardware Shutdown
        2. 6.3.1.2 Hardware Config Modes
        3. 6.3.1.3 Software Power Modes Control and Software Reset
        4. 6.3.1.4 Efficiency and power saving modes
          1. 6.3.1.4.1 Noise Gate
          2. 6.3.1.4.2 Music Efficiency Mode
          3. 6.3.1.4.3 VDD Y-bridge
          4. 6.3.1.4.4 Class-H Boost
        5. 6.3.1.5 2S Battery Mode
        6. 6.3.1.6 External PVDD Mode
      2. 6.3.2 Faults and Status
        1. 6.3.2.1 Interrupt generation and clearing
    4. 6.4 Feature Description
      1. 6.4.1  PurePath™ Console 3 Software
      2. 6.4.2  Playback Signal Path
        1. 6.4.2.1 Digital Volume Control and Amplifier Output Level
        2. 6.4.2.2 High Pass Filter
        3. 6.4.2.3 Class-D Amplifier
        4. 6.4.2.4 Supply Tracking Limiters with Brown Out Prevention
          1. 6.4.2.4.1 Voltage Limiter and Clipping protection
        5. 6.4.2.5 Tone Generator
      3. 6.4.3  Digital Audio Serial Interface
        1. 6.4.3.1 Digital Loopback
      4. 6.4.4  Internal Boost
      5. 6.4.5  Boost Share
      6. 6.4.6  External Class-H Boost Controller
      7. 6.4.7  Supply Voltage Monitors
      8. 6.4.8  Thermal Protection
      9. 6.4.9  Clocks and PLL
        1. 6.4.9.1 Auto clock based wakeup and clock errors
      10. 6.4.10 Digital IO pins
    5. 6.5 Programming
      1. 6.5.1 I2C Control Interface
      2. 6.5.2 I2C Address Selection
      3. 6.5.3 General I2C Operation
      4. 6.5.4 I2C Single-Byte and Multiple-Byte Transfers
      5. 6.5.5 I2C Single-Byte Write
      6. 6.5.6 I2C Multiple-Byte Write
      7. 6.5.7 I2C Single-Byte Read
      8. 6.5.8 I2C Multiple-Byte Read
  8. 7 Register Maps
    1. 7.1  PAGE 0 Registers
    2. 7.2  PAGE 1 Registers
    3. 7.3  PAGE 2 Registers
    4. 7.4  PAGE 3 Registers
    5. 7.5  PAGE 4 Registers
    6. 7.6  PAGE 5 Registers
    7. 7.7  PAGE 6 Registers
    8. 7.8  PAGE 7 Registers
    9. 7.9  PAGE 8 Registers
    10. 7.10 BOOK100 PAGE9 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Mono/Stereo Configuration
        2. 8.2.2.2 Boost Converter Passive Devices
        3. 8.2.2.3 EMI Passive Devices
        4. 8.2.2.4 Miscellaneous Passive Devices
      3. 8.2.3 Application Performance Plots
    3. 8.3 What to Do and What Not to Do
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

TA = 25°C, VBAT = 3.6V, VBAT2S = 7.2V (2S mode enabled), PVDD = 12V ( External PVDD mode enabled), VDD = 1.8V, IOVDD = 1.8V, RL = 8Ω + 33µH, LBOOST(1S Boost mode) = 1µH, Fin = 1kHz, Fs = 48kHz, Gain = 21dBV, BST_ILIM (1S Boost mode) = 5.1A, BST_ILIM (2S Boost, HW mode) = 4.1A, BST_ILIM (2S Boost, I2C mode) = 5.1A, SDZ=1, Noise gate disabled, Class-D edge rate set to 2V/ns, I2C mode of operation, Measured filter free with an Audio Precision using 22Hz to 20kHz un-weighted bandwidth (unless otherwise noted).(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AMPLIFIER PERFORMANCE - INTERNAL BOOST 1S Mode
POUT Maximum Output Power - 1% THD+N RL = 8 Ω + 33 µH 6.4 W
RL = 4 Ω + 33 µH 6.6 W
RL = 8 Ω + 33 µH, VBAT = 4.4V 8.0 W
RL = 4 Ω + 33 µH, VBAT = 4.4V 8.2 W
POUT Maximum Output Power - 10% THD+N RL = 8 Ω + 33 µH, VBAT = 4.4V 9.5 W
RL = 4 Ω + 33 µH, VBAT = 4.4V 9.8 W
ηSYSTEM_1W System Efficiency at POUT = 1.0W RL = 8 Ω + 33 µH 86.7 %
RL = 4 Ω + 33 µH 85 %
RL = 8 Ω + 33 µH, VBAT = 4.4V 87.8 %
RL = 4 Ω + 33 µH, VBAT = 4.4V 86.7 %
ηSYSTEM_MAX_POUT System Efficiency at 1% THD+N power Level RL = 8 Ω + 33 µH 72.6 %
RL = 4 Ω + 33 µH 71.8 %
RL = 8 Ω + 33 µH, VBAT = 4.4V 76.6 %
RL = 4 Ω + 33 µH, VBAT = 4.4V 76.5 %
VN Idle channel Noise A-Weighted, Gain = 6dBV (Receiver Mode), DAC-Running 4.2 µV
A-Weighted, Gain = 21dBV (Speaker Mode), DAC-Running 14.4 µV
DNR Dynamic Range A-Weighted, -60 dBFS Method, RL = 8 Ω + 33 µH, Gain = 6dBV (Receiver Mode) 113.8 dB
A-Weighted, -60 dBFS Method, RL = 8 Ω + 33 µH, Gain = 21dBV (Speaker Mode) 113.7 dB
THD+N Total Harmonic distortion + Noise POUT = 1 W, RL = 8 Ω + 33 µH 0.003 %
POUT = 1 W, RL = 4 Ω + 33 µH 0.004 %
KCP Click and pop performance All dynamic power up/downs of audio channel except for faults. Includes in/out of mute, power up and power down, noise gate mode entry and exit. Measured as peak A-weighted voltage. RL = 8 Ω + 33 µH, Input = digital silence –67 dBV
BW Amplifier input signal Bandwidth fs ≥ 96ksps, Gain error < Pass-Band Ripple 40 kHz
VFS Full scale equivalent Voltage Measured at -6dBFS Input, Gain = 6dBV (Receiver Mode) 2.00 VRMS
AGAIN Audio channel Gain programmability range Gain programmability in steps of 0.5dB 0 21 dBV
AGAIN_ERR Amplifier Gain error POUT = 1W ±0.1 dB
POUT = 0.25W, Gain = 6dBV (Receiver Mode) ±0.1 dB
VOS Output Offset Voltage Idle channel –1 1 mV
Idle channel, Gain = 6dBV (Receiver Mode) –1 1 mV
FPWM Class-D PWM switching Frequency Average clock frequency 384 kHz
PSRRVBAT VBAT power-supply rejection ratio VBAT + 200 mVpp, fripple = 217 Hz 118 dB
VBAT + 200 mVpp, fripple = 1 kHz 115 dB
VBAT + 200 mVpp, fripple = 20 kHz 80 dB
PSRRVDD VDD power-supply rejection ratio VDD + 200 mVpp, fripple = 217 Hz 113 dB
VDD + 200 mVpp, fripple = 1 kHz 113 dB
VDD + 200 mVpp, fripple = 20 kHz 91 dB
MUTE_ATTN Mute Attenuation Device is MUTE mode. DAC modulator running 113 dB
AMPLIFIER PERFORMANCE - INTERNAL BOOST 2S Mode
POUT_BOOST_2S Maximum Output Power - 1% THD+N RL = 8 Ω + 33 µH 10.0 W
RL = 4 Ω + 33 µH 12.8 W
RL = 8 Ω + 33 µH, VBAT2S = 8.4V 10.4 W
RL = 4 Ω + 33 µH, VBAT2S = 8.4V 14.5 W
POUT_BOOST_2S Maximum Output Power - 10% THD+N RL = 8 Ω + 33 µH, VBAT2S = 8.4V 12.6 W
RL = 4 Ω + 33 µH, VBAT2S = 8.4V 17.5 W
ηSYSTEM_1W_2S System Efficiency at POUT = 1.0W RL = 8 Ω + 33 µH 89.9 %
RL = 8 Ω + 33 µH, VBAT2S = 8.4V 89.5 %
RL = 4 Ω + 33 µH 86.2 %
RL = 4 Ω + 33 µH, VBAT2S = 8.4V 85.8 %
ηSYSTEM_MAX_POUT_2S System Efficiency at 1% THD+N power Level RL = 8 Ω + 33 µH 85 %
RL = 8 Ω + 33 µH, VBAT2S= 8.4V 86.5 %
RL = 4 Ω + 33 µH 77.4 %
RL = 4 Ω + 33 µH, VBAT2S = 8.4V 78.0 %
VN_2S Idle channel Noise A-Weighted, Gain = 6dBV (Receiver Mode), DAC-Running 7.0 µV
A-Weighted, Gain = 21dBV (Speaker Mode), DAC-Running 14.4 µV
DNR_2S Dynamic Range A-Weighted, -60 dBFS Method, Gain = 6dBV (Receiver Mode) 108.9 dB
A-Weighted, -60 dBFS Method, Gain = 21dBV (Speaker Mode) 114.4 dB
THD+N_2S Total Harmonic distortion + Noise POUT = 1 W, RL = 8 Ω + 33 µH, fin = 1 kHz 0.003 %
POUT = 1 W, RL = 4 Ω + 33 µH, fin = 1 kHz 0.003 %
POUT = 0.25 W, RL = 8 Ω + 33 µH, fin = 1 kHz, Gain = 6dBV (Receiver Mode) 0.005 %
KCP_2S Click and pop performance All dynamic power up/downs of audio channel except for faults. Includes In/Out of Mute, Power Up and power Down, Noise Gate mode entry and Exit. Measured at Peak A-weighted Voltage. RL = 8 Ω + 33 µH, Input = Digital silence. –68 dBV
PSRRVBAT2S VBAT2S power-supply rejection ratio VBAT2S = 7.2 V + 200 mVpp, fripple = 217 Hz 115 dB
VBAT2S = 7.2 V + 200 mVpp, fripple = 1 kHz 115 dB
VBAT2S = 7.2 V + 200 mVpp, fripple = 20 kHz 90 dB
PSRRVBAT_2S VBAT power-supply rejection ratio VBAT = 3.6 V + 200 mVpp, fripple = 217 Hz 115 dB
VBAT = 3.6 V + 200 mVpp, fripple = 1 kHz 115 dB
VBAT = 3.6 V + 200 mVpp, fripple = 20 kHz 90 dB
PSRRVDD_2S VDD power-supply rejection ratio VDD = 1.8 V + 200 mVpp, fripple = 217 Hz 110 dB
VDD = 1.8 V + 200 mVpp, fripple = 1 kHz 110 dB
VDD = 1.8 V + 200 mVpp, fripple = 20 kHz 90 dB
AMPLIFIER PERFORMANCE - EXTERNAL PVDD Mode
POUT_EXT_PVDD Maximum Output Power - 1% THD+N RL = 8 Ω + 33 µH 8.2 W
RL = 4 Ω + 33 µH 14.6 W
RL = 8 Ω + 33 µH, PVDD = 15V  11.2 W
RL = 4 Ω + 33 µH, PVDD = 15V 19 W
POUT_EXT_PVDD Maximum Output Power - 10% THD+N RL = 8 Ω + 33 µH 10.3 W
RL = 4 Ω + 33 µH 18.0 W
ηSYSTEM__EXT_1W System Efficiency at POUT = 1.0W RL = 8 Ω + 33 µH 88.1 %
RL = 4 Ω + 33 µH 84.2 %
ηSYSTEM_EXT_MAX_POUT System Efficiency at 1% THD+N power Level RL = 8 Ω + 33 µH 93.2 %
RL = 4 Ω + 33 µH 88.5 %
VN_EXT Idle channel Noise A-Weighted, Gain = 21dBV (Speaker Mode), DAC-Running 14.2 µV
DNR_EXT Dynamic Range A-Weighted, -60 dBFS Method, RL = 8 Ω + 33 µH 114.4 dB
THD+N_EXT Total Harmonic distortion + Noise POUT = 1 W, RL = 8 Ω + 33 µH 0.003 %
POUT = 1 W, RL = 4 Ω + 33 µH 0.004 %
KCP_EXT Click and pop performance All dynamic power up/downs of audio channel except for faults. Includes In/Out of Mute, Power Up and power Down, Noise Gate mode entry and Exit. Measured at Peak A-weighted Voltage. RL = 8 Ω + 33 µH, Input = Digital Silence –68 dBV
VOS_EXT Output Offset Voltage Idle channel –1 1 mV
PSRRPVDD_EXT PVDD power-supply rejection ratio PVDD + 200 mVpp, fripple = 217 Hz 119 dB
PVDD + 200 mVpp, fripple = 1 kHz 115 dB
PVDD + 200 mVpp, fripple = 20 kHz 91 dB
PSRRVBAT_EXT VBAT power-supply rejection ratio VBAT + 200 mVpp, fripple = 217 Hz 118 dB
VBAT + 200 mVpp, fripple = 1 kHz 116 dB
VBAT + 200 mVpp, fripple = 20 kHz 102 dB
PSRRVDD_EXT VDD power-supply rejection ratio VDD + 200 mVpp, fripple = 217 Hz 113 dB
VDD + 200 mVpp, fripple = 1 kHz 113 dB
VDD + 200 mVpp, fripple = 20 kHz 91 dB
Boost Converter
VBOOST_RANGE Max Output Voltage programmability Range Programmable in steps of 66mV 5.5 14.75 V
VBOOST_STEP Class-H Output Voltage Step Size 33 mV
VBOOST Output Boost Voltage IO = 0.1A. Average output value. VBOOST_MAX_CTRL = max value 14.9 V
IBOOST_CL Peak Input Current Limit BST_ILIM = Max Setting 5.1 A
IBOOST_CL Peak Input Current Limit BST_ILIM = Min Setting  1.5 A
Peak Input Current Limit Programmable step size 39.1 mA
Boost Converter 2S Mode of operation
VBOOST_RANGE Output Voltage Range Programmable in steps of 66mV 10 14.75 V
VBOOST_STEP Class-H Output Voltage Step Size 33 mV
IBOOST_CL Peak Input Current Limit (I2C mode) Max Setting 5.1 A
IBOOST_CL Peak Input Current Limit Min Setting 1.5 A
TDM Serial Port
PCM Sample Rates and FSYNC Input Frequency 16 192 kHz
SBCLK Input Frequency I2S/TDM Operation 0.512 24.57 MHz
SBCLK Maximum Input Jitter RMS Jitter below 40 kHz that can be tolerated without performance degradation 0.5 ns
RMS Jitter above 40 kHz that can be tolerated without performance degradation 5 ns
SBCLK Cycles per FSYNC in I2S and TDM Modes Values: 64, 96, 128, 192, 256, 384 and 512 64 512 Cycles
PCM Playback Characteristics to fs ≤ 48 kHz
Fs Sample Rates 16 48 kHz
Audio Channel Passband LPF Corner Ripple < pass-band ripple 0.454 fs
Audio Channel Passband Ripple 20 Hz to LPF cutoff ± 0.1 dB
Audio Channel Stop Band Attenuation ≥ 0.55 fs 60 dB
≥ 1 fs 65 dB
Audio Channel Group Delay Fin = 1kHz, Lowest latency mode (Y-bridge, Class-H, Noise Gate disabled)  8.5 1/fs
Fin = 1kHz, Class-H disabled 16.5 1/fs
Fin = 1kHz, Class-H enabled 31.5 1/fs
DC to 20kHz, Lowest latency mode (HPF bypassed, Y-bridge, Class-H, Noise Gate disabled) 13 1/fs
DC to 20kHz, HPF bypassed, Class-H disabled 21 1/fs
DC to 20kHz, HPF bypassed, Class-H enabled 37 1/fs
PCM Playback Characteristics to fs > 48 kHz
Fs Sample Rates 88.2 192 kHz
Audio Channel Passband LPF Corner fs = 96 kHz 0.469 fs
fs = 192 kHz 0.234 fs
Audio Channel Passband Ripple 20 Hz to LPF cutoff ± 0.2 dB
Audio Channel Stop Band Attenuation fs = 96 kHz, fin ≥ 0.55 fs 60 dB
fs = 96 kHz, fin ≥ 1 fs 65 dB
fs = 192 kHz, 0.55 fs ≥ fin ≥ 0.275 fs 60 dB
Audio Channel Group Delay Fin = 1kHz, Fs = 96kHz, Lowest latency mode (Y-bridge, Class-H, Noise Gate disabled)  11 1/fs
Fin = 1kHz, Fs = 96kHz, Class-H disabled 6.7 1/fs
Fin = 1kHz, Fs = 96kHz, Class-H enabled 56.7 1/fs
DC to 20kHz, Fs = 96kHz, Lowest latency mode (HPF bypassed, Y-bridge, Class-H, Noise Gate disabled) 11.5 1/fs
DC to 40kHz, Fs=96kHz, HPF bypassed, Class-H disabled 28.6 1/fs
DC to 40kHz, Fs=192 kHz, HPF bypassed, Class-H enabled 117.8 1/fs
Protection Circuits
Thermal shutdown temperature 140 °C
Thermal shutdown retry time 1.5 s
VBAT undervoltage lockout threshold (UVLO) UVLO is asserted 1.9 V
UVLO is released 2.3 V
VDD undervoltage lockout threshold (UVLO) UVLO is asserted 1.4 V
UVLO is released 1.6 V
PVDD undervoltage lockout threshold (UVLO) UVLO is asserted, external PVDD mode only 2.6 V
UVLO is released, external PVDD mode only 2.8 V
PVDD overvoltage lockout threshold (OVLO) OVLO is asserted, OVLO protection enabled.  16 V
Power up/down Time
TSTDBY Turn ON time from SDZ Asserted to device ready for i2c Command 300 us
TACTIVE Turn ON time from release of Software Shutdown to Amplifier output Active Volume ramping disabled 1.6 ms
Volume ramping enabled 3.9 ms
TTURNOFF Turn OFF time from assertion of Software Shutdown to Amplifier output Hi-Z Volume ramping disabled 0.2 ms
Volume ramping enabled 13.9 ms
Current Consumption - Internal Boost Mode(1)
IQ_HW_SD Current consumption in Hardware Shutdown VBAT, SDZ=0 0.1 uA
VDD, SDZ=0 0.2 uA
IOVDD, SDZ=0 0.1 uA
IQ_SW_SD Current consumption in Software Shutdown VBAT, All clocks Stopped 0.1 uA
VDD, All clocks Stopped 12 uA
IOVDD, All clocks Stopped 0.1 uA
IQ_NG Current consumption in Idle channel  VBAT, POUT = 0, Noise Gate enabled 0.19 mA
VDD, POUT = 0, Noise Gate enabled 2.3 mA
IOVDD, POUT = 0, Noise Gate enabled 0.1 mA
Total Power, POUT = 0, Noise Gate enabled 4.8 mW
IQ_IDLE Current consumption in Idle channel VBAT, POUT = 0, Noise gate disabled 0.62 mA
VDD, POUT = 0, Noise gate disabled 6 mA
IOVDD, POUT = 0, Noise gate disabled 0.1 mA
Total Power, POUT = 0, Noise gate disabled 13.1 mW
Current Consumption - Internal Boost Mode 2S Mode(1)
IQ_HW_SD Current consumption in Hardware Shutdown VBAT, SDZ=0 0.1 uA
VBAT2S, SDZ=0 0.1 uA
VDD, SDZ=0 0.2 uA
IOVDD, SDZ=0 0.1 uA
IQ_SW_SD Current consumption in Software Shutdown VBAT, All clocks Stopped 0.1 uA
VBAT2S, All clocks Stopped 0.1 uA
VDD, All clocks Stopped 12 uA
IOVDD, All clocks Stopped 0.1 uA
IQ_NG Current consumption in Idle channel  VBAT, POUT = 0, Noise gate enabled 0.2 mA
VBAT2S, POUT = 0, Noise gate enabled 0.1 mA
VDD, POUT = 0, Noise gate enabled 2.3 mA
IOVDD, POUT = 0, Noise gate enabled 0.1 mA
Total Power, POUT = 0, Noise gate enabled 5.1 mW
IQ_IDLE Current consumption in Idle Channel VBAT, POUT = 0, Noise gate disabled 0.5 mA
VBAT2S, POUT = 0, Noise gate disabled 0.35 mA
VDD, POUT = 0, Noise gate disabled 6 mA
IOVDD, POUT = 0, Noise gate disabled 0.1 mA
Total Power, POUT = 0, Noise gate disabled 15.1 mW
Current Consumption - External PVDD Mode(1)
IQ_HW_SD Current consumption in Hardware Shutdown PVDD, SDZ=0 0.1 uA
VBAT, SDZ=0 0.1 uA
VDD, SDZ=0 0.2 uA
IOVDD, SDZ=0 0.1 uA
IQ_SW_SD Current consumption in Software Shutdown PVDD, All clocks Stopped 0.1 uA
VBAT, All clocks Stopped 0.1 uA
VDD, All clocks Stopped 12 uA
IOVDD, All clocks Stopped 0.1 uA
IQ_NG Current consumption in Idle channel  PVDD, POUT = 0, Noise gate enabled 0.1 mA
VBAT, POUT = 0, Noise gate enabled 0.15 mA
VDD, POUT = 0, Noise gate enabled 2.2 mA
IOVDD, POUT = 0, Noise gate enabled 0.1 mA
Total Power, POUT = 0, Noise gate enabled 5.3 mW
IQ_IDLE Current consumption in Idle channel PVDD, POUT = 0, Noise gate disabled 0.2 mA
VBAT, POUT = 0, Noise gate disabled 0.5 mA
VDD, POUT = 0, Noise gate disabled 6 mA
IOVDD, POUT = 0, Noise gate disabled 0.1 mA
Total Power, POUT = 0, Noise gate disabled 14.7 mW
DIGITAL IOs
VIH High-level digital input logic voltage threshold All digital pins  0.7 x IOVDD V
VIL Low-level digital input logic voltage threshold All digital pins 0.3 x IOVDD V
VOH High-level digital output voltage All digital pins except SDA, SCL and IRQZ; IOH = 100µA IOVDD - 0.2 V V
VOL Low-level digital output voltage All digital pins except SDA, SCL and IRQZ; IOL = -100µA 0.2 V
VOL(I2C) Low-level digital output voltage SDA and SCL; IOL = -1mA 0.2 x IOVDD V
VOL(IRQZ) Low-level digital output voltage for open drain output IRQZ pin; IOL = -1mA 0.2 V
IIH(1) Input logic-high leakage for digital inputs All digital pins; Input = IOVDD. -1 1 µA
IIL(1) Input logic-low leakage for digital inputs All digital pins; Input = GND -1 1 µA
CIN Input capacitance for digital inputs All digital pins 5 pF
RPD Pull down resistance for digital input/IO pins when asserted on All digital pins. Pull down resistance option enabled 18 kΩ
(1) Errata: Additional 2mA to 3mA current consumption expected if IRQZ signal is pulled high. Read more details in section "what to do and what not to do".