SLOSE75B February   2022  – March 2023 TAS2780

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Timing Requirements
    7. 6.7 TDM Port Timing Requirements
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1  Overview
    2. 8.2  Functional Block Diagram
    3. 8.3  Feature Description
      1. 8.3.1 Device Address Selection
      2. 8.3.2 Register Organization
    4. 8.4  Device Functional Modes
      1. 8.4.1  TDM Port
      2. 8.4.2  Playback Signal Path
        1. 8.4.2.1  High Pass Filter
        2. 8.4.2.2  Amplifier Inversion
        3. 8.4.2.3  Digital Volume Control and Amplifier Output Level
          1. 8.4.2.3.1 Safe Mode
        4. 8.4.2.4  VBAT1S Supply
        5. 8.4.2.5  Low Voltage Signaling (LVS)
        6. 8.4.2.6  Y-Bridge
        7. 8.4.2.7  Noise Gate
        8. 8.4.2.8  Supply Tracking Limiter with Brown Out Prevention
          1. 8.4.2.8.1 Supply Tracking Limiter (STL)
          2. 8.4.2.8.2 Brownout Prevention (BOP)
        9. 8.4.2.9  Low Battery Tracking Limiter (LBTL)
        10. 8.4.2.10 Inter Chip Gain Alignment (ICGA)
          1. 8.4.2.10.1 Inter-Chip Communication (ICC) Pin
        11. 8.4.2.11 Class-D Settings
          1. 8.4.2.11.1 Synchronization
          2. 8.4.2.11.2 Output Slew Rate Control
      3. 8.4.3  SAR ADC
      4. 8.4.4  Current and Voltage (IV) Sense
      5. 8.4.5  Post Filter Feed-Back (PFFB)
      6. 8.4.6  Load Diagnostics
      7. 8.4.7  Thermal Foldback
      8. 8.4.8  Over Power Protection
      9. 8.4.9  Low Battery Protection
      10. 8.4.10 Clocks and PLL
      11. 8.4.11 Ultrasonic
      12. 8.4.12 Echo Reference
    5. 8.5  Operational Modes
      1. 8.5.1 Hardware Shutdown
      2. 8.5.2 Mode Control and Software Reset
      3. 8.5.3 Software Shutdown
      4. 8.5.4 Mute Mode
      5. 8.5.5 Active Mode
      6. 8.5.6 Diagnostic Mode
      7. 8.5.7 Noise Gate Mode
    6. 8.6  Faults and Status
      1. 8.6.1 Faults and Status Over TDM
      2. 8.6.2 Temperature Warnings
    7. 8.7  Power Sequencing Requirements
    8. 8.8  Digital Input Pull Downs
    9. 8.9  Register Map
      1. 8.9.1   Register Summary Table Page=0x00
      2. 8.9.2   Register Summary Table Page=0x01
      3. 8.9.3   Register Summary Table Page=0x04
      4. 8.9.4   Register Summary Table Page=0xFD
      5. 8.9.5   Note and Legend
      6. 8.9.6   PAGE (page=0x00 address=0x00) [reset=00h]
      7. 8.9.7   SW_RESET (page=0x00 address=0x01) [reset=00h]
      8. 8.9.8   MODE_CTRL (page=0x00 address=0x02) [reset=1Ah]
      9. 8.9.9   CHNL_0 (page=0x00 address=0x03) [reset=28h]
      10. 8.9.10  DC_BLK0 (page=0x00 address=0x04) [reset=21h]
      11. 8.9.11  DC_BLK1 (page=0x00 address=0x05) [reset=41h]
      12. 8.9.12  MISC_CFG1 (page=0x00 address=0x06) [reset=00h]
      13. 8.9.13  MISC_CFG2 (page=0x00 address=0x07) [reset=20h]
      14. 8.9.14  TDM_CFG0 (page=0x00 address=0x08) [reset=09h]
      15. 8.9.15  TDM_CFG1 (page=0x00 address=0x09) [reset=02h]
      16. 8.9.16  TDM_CFG2 (page=0x00 address=0x0A) [reset=0Ah]
      17. 8.9.17  LIM_MAX_ATTN (page=0x00 address=0x0B) [reset=80h]
      18. 8.9.18  TDM_CFG3 (page=0x00 address=0x0C) [reset=10h]
      19. 8.9.19  TDM_CFG4 (page=0x00 address=0x0D) [reset=13h]
      20. 8.9.20  TDM_CFG5 (page=0x00 address=0x0E) [reset=42h]
      21. 8.9.21  TDM_CFG6 (page=0x00 address=0x0F) [reset=40h]
      22. 8.9.22  TDM_CFG7 (page=0x00 address=0x10) [reset=04h]
      23. 8.9.23  TDM_CFG8 (page=0x00 address=0x11) [reset=05h]
      24. 8.9.24  TDM_CFG9 (page=0x00 address=0x12) [reset=06h]
      25. 8.9.25  TDM_CFG10 (page=0x00 address=0x13) [reset=08h]
      26. 8.9.26  TDM_CFG11 (page=0x00 address=0x14) [reset=0Ah]
      27. 8.9.27  ICC_CNFG2 (page=0x00 address=0x15) [reset=00h]
      28. 8.9.28  TDM_CFG12 (page=0x00 address=0x16) [reset=12h]
      29. 8.9.29  ICLA_CFG0 (page=0x00 address=0x17) [reset=0Ch]
      30. 8.9.30  ICLA_CFG1 (page=0x00 address=0x18) [reset=00h]
      31. 8.9.31  DG_0 (page=0x00 address=0x19) [reset=0Dh]
      32. 8.9.32  DVC (page=0x00 address=0x1A) [reset=00h]
      33. 8.9.33  LIM_CFG0 (page=0x00 address=0x1B) [reset=62h]
      34. 8.9.34  LIM_CFG1 (page=0x00 address=0x1C) [reset=32h]
      35. 8.9.35  BOP_CFG0 (page=0x00 address=0x1D) [reset=40h]
      36. 8.9.36  BOP_CFG1 (page=0x00 address=0x1E) [reset=32h]
      37. 8.9.37  BOP_CFG2 (page=0x00 address=0x1F) [reset=02h]
      38. 8.9.38  BOP_CFG3 (page=0x00 address=0x20) [reset=06h]
      39. 8.9.39  BOP_CFG4 (page=0x00 address=0x21) [reset=2Ch]
      40. 8.9.40  BOP_CFG5 (page=0x00 address=0x22) [reset=4Ch]
      41. 8.9.41  BOP_CFG6 (page=0x00 address=0x23) [reset=20h]
      42. 8.9.42  BOP_CFG7 (page=0x00 address=0x24) [reset=02h]
      43. 8.9.43  BOP_CFG8 (page=0x00 address=0x25) [reset=06h]
      44. 8.9.44  BOP_CFG9 (page=0x00 address=0x26) [reset=32h]
      45. 8.9.45  BOP_CFG10 (page=0x00 address=0x27) [reset=46h]
      46. 8.9.46  BOP_CFG11 (page=0x00 address=0x28) [reset=20h]
      47. 8.9.47  BOP_CFG12 (page=0x00 address=0x29) [reset=02h]
      48. 8.9.48  BOP_CFG13 (page=0x00 address=0x2A) [reset=06h]
      49. 8.9.49  BOP_CFG14 (page=0x00 address=0x2B) [reset=38h]
      50. 8.9.50  BOP_CFG15 (page=0x00 address=0x2C) [reset=40h]
      51. 8.9.51  BOP_CFG17 (page=0x00 address=0x2D) [reset=20h]
      52. 8.9.52  BOP_CFG18 (page=0x00 address=0x2E) [reset=02h]
      53. 8.9.53  BOP_CFG19 (page=0x00 address=0x2F) [reset=06h]
      54. 8.9.54  BOP_CFG20 (page=0x00 address=0x30) [reset=3Eh]
      55. 8.9.55  BOP_CFG21 (page=0x00 address=0x31) [reset=37h]
      56. 8.9.56  BOP_CFG22 (page=0x00 address=0x32) [reset=20h]
      57. 8.9.57  BOP_CFG23 (page=0x00 address=0x33) [reset=FFh]
      58. 8.9.58  BOP_CFG24 (page=0x00 address=0x34) [reset=E6h]
      59. 8.9.59  NG_CFG0 (page=0x00 address=0x35) [reset=BDh]
      60. 8.9.60  NG_CFG1 (page=0x00 address=0x36) [reset=ADh]
      61. 8.9.61  LVS_CFG0 (page=0x00 address=0x37) [reset=A8h]
      62. 8.9.62  DIN_PD (page=0x00 address=0x38) [reset=03h]
      63. 8.9.63  INT_MASK0 (page=0x00 address=0x3B) [reset=FCh]
      64. 8.9.64  INT_MASK1 (page=0x00 address=0x3C) [reset=BFh]
      65. 8.9.65  INT_MASK4 (page=0x00 address=0x3D) [reset=DFh]
      66. 8.9.66  INT_MASK2 (page=0x00 address=0x40) [reset=F6h]
      67. 8.9.67  INT_MASK3 (page=0x00 address=0x41) [reset=00h]
      68. 8.9.68  INT_LIVE0 (page=0x00 address=0x42) [reset=00h]
      69. 8.9.69  INT_LIVE1 (page=0x00 address=0x43) [reset=00h]
      70. 8.9.70  INT_LIVE1_0 (page=0x00 address=0x44) [reset=00h]
      71. 8.9.71  INT_LIVE2 (page=0x00 address=0x47) [reset=00h]
      72. 8.9.72  INT_LIVE3 (page=0x00 address=0x48) [reset=00h]
      73. 8.9.73  INT_LTCH0 (page=0x00 address=0x49) [reset=00h]
      74. 8.9.74  INT_LTCH1 (page=0x00 address=0x4A) [reset=00h]
      75. 8.9.75  INT_LTCH1_0 (page=0x00 address=0x4B) [reset=00h]
      76. 8.9.76  INT_LTCH2 (page=0x00 address=0x4F) [reset=00h]
      77. 8.9.77  INT_LTCH3 (page=0x00 address=0x50) [reset=00h]
      78. 8.9.78  INT_LTCH4 (page=0x00 address=0x51) [reset=00h]
      79. 8.9.79  VBAT_MSB (page=0x00 address=0x52) [reset=00h]
      80. 8.9.80  VBAT_LSB (page=0x00 address=0x53) [reset=00h]
      81. 8.9.81  PVDD_MSB (page=0x00 address=0x54) [reset=00h]
      82. 8.9.82  PVDD_LSB (page=0x00 address=0x55) [reset=00h]
      83. 8.9.83  TEMP (page=0x00 address=0x56) [reset=00h]
      84. 8.9.84  INT_CLK_CFG (page=0x00 address=0x5C) [reset=19h]
      85. 8.9.85  MISC_CFG3 (page=0x00 address=0x5D) [reset=80h]
      86. 8.9.86  CLOCK_CFG (page=0x00 address=0x60) [reset=0Dh]
      87. 8.9.87  IDLE_IND (page=0x00 address=0x63) [reset=48]
      88. 8.9.88  SAR_SAMP (page=0x00 address=0x64) [reset=84h]
      89. 8.9.89  MISC_CFG4 (page=0x00 address=0x65) [reset=08]
      90. 8.9.90  IDLE_CFG (page=0x00 address=0x67) [reset=00h]
      91. 8.9.91  CLK_CFG (page=0x00 address=0x68) [reset=7Fh]
      92. 8.9.92  LV_EN_CFG (page=0x00 address=0x6A) [reset=12h]
      93. 8.9.93  NG_CFG2 (page=0x00 address=0x6B) [reset=43h]
      94. 8.9.94  NG_CFG3 (page=0x00 address=0x6C) [reset=00h]
      95. 8.9.95  NG_CFG4 (page=0x00 address=0x6D) [reset=00h]
      96. 8.9.96  NG_CFG5 (page=0x00 address=0x6E) [reset=1Ah]
      97. 8.9.97  NG_CFG6 (page=0x00 address=0x6F) [reset=00h]
      98. 8.9.98  NG_CFG7 (page=0x00 address=0x70) [reset=96h]
      99. 8.9.99  PVDD_UVLO (page=0x00 address=0x71) [reset=02h]
      100. 8.9.100 DMD (page=0x00 address=0x73) [reset=00h]
      101. 8.9.101 I2C_CKSUM (page=0x00 address=0x7E) [reset=00h]
      102. 8.9.102 BOOK (page=0x00 address=0x7F) [reset=00h]
      103. 8.9.103 INIT_0 (page=0x01 address=0x17) [reset=D0h]
      104. 8.9.104 LSR (page=0x01 address=0x19) [reset=40h]
      105. 8.9.105 INIT_1 (page=0x01 address=0x21) [reset=08h]
      106. 8.9.106 INIT_2 (page=0x01 address=0x35) [reset=75h]
      107. 8.9.107 INT_LDO (page=0x01 address=0x36) [reset=08h]
      108. 8.9.108 SDOUT_HIZ_1 (page=0x01 address=0x3D) [reset=00h]
      109. 8.9.109 SDOUT_HIZ_2 (page=0x01 address=0x3E) [reset=00h]
      110. 8.9.110 SDOUT_HIZ_3 (page=0x01 address=0x3F) [reset=00h]
      111. 8.9.111 SDOUT_HIZ_4 (page=0x01 address=0x40) [reset=00h]
      112. 8.9.112 SDOUT_HIZ_5 (page=0x01 address=0x41) [reset=00h]
      113. 8.9.113 SDOUT_HIZ_6 (page=0x01 address=0x42) [reset=00h]
      114. 8.9.114 SDOUT_HIZ_7 (page=0x01 address=0x43) [reset=00h]
      115. 8.9.115 SDOUT_HIZ_8 (page=0x01 address=0x44) [reset=00h]
      116. 8.9.116 SDOUT_HIZ_9 (page=0x01 address=0x45) [reset=00h]
      117. 8.9.117 TG_EN (page=0x01 address=0x47) [reset=AB]
      118. 8.9.118 EDGE_CTRL (page=0x01 address=0x4C) [reset=00h]
      119. 8.9.119 DG_DC_VAL1 (page=0x04 address=0x08) [reset=40h]
      120. 8.9.120 DG_DC_VAL2 (page=0x04 address=0x09) [reset=26h]
      121. 8.9.121 DG_DC_VAL3 (page=0x04 address=0x0A) [reset=40h]
      122. 8.9.122 DC_DG_VAL4 (page=0x04 address=0x0B) [reset=00h]
      123. 8.9.123 LIM_TH_MAX1 (page=0x04 address=0x0C) [reset=68h]
      124. 8.9.124 LIM_TH_MAX2 (page=0x04 address=0x0D) [reset=00h]
      125. 8.9.125 LIM_TH_MAX3 (page=0x04 address=0x0E) [reset=00h]
      126. 8.9.126 LIM_TH_MAX4 (page=0x04 address=0x0F) [reset=00h]
      127. 8.9.127 LIM_TH_MIN1 (page=0x04 address=0x10) [reset=28h]
      128. 8.9.128 LIM_TH_MIN2 (page=0x04 address=0x11) [reset=00h]
      129. 8.9.129 LIM_TH_MIN3 (page=0x04 address=0x12) [reset=00h]
      130. 8.9.130 LIM_TH_MIN4 (page=0x04 address=0x13) [reset=00h]
      131. 8.9.131 LIM_INF_PT1 (page=0x04 address=0x14) [reset=56h]
      132. 8.9.132 LIM_INF_PT2 (page=0x04 address=0x15) [reset=66h]
      133. 8.9.133 LIM_INF_PT3 (page=0x04 address=0x16) [reset=66h]
      134. 8.9.134 LIM_INF_PT4 (page=0x04 address=0x17) [reset=00h]
      135. 8.9.135 LIM_SLOPE1 (page=0x04 address=0x18) [reset=10h]
      136. 8.9.136 LIM_SLOPE2 (page=0x04 address=0x19) [reset=00h]
      137. 8.9.137 LIM_SLOPE3 (page=0x04 address=0x1A) [reset=00h]
      138. 8.9.138 LIM_SLOPE4 (page=0x04 address=0x1B) [reset=00h]
      139. 8.9.139 TF_HLD1 (page=0x04 address=0x1C) [reset=00h]
      140. 8.9.140 TF_HLD2 (page=0x04 address=0x1D) [reset=00h]
      141. 8.9.141 TF_HLD3 (page=0x04 address=0x1E) [reset=64h]
      142. 8.9.142 TF_HLD4 (page=0x04 address=0x1F) [reset=00h]
      143. 8.9.143 TF_RLS1 (page=0x04 address=0x20) [reset=40h]
      144. 8.9.144 TF_RLS2 (page=0x04 address=0x21) [reset=BDh]
      145. 8.9.145 TF_RLS3 (page=0x04 address=0x22) [reset=B8h]
      146. 8.9.146 TF_RLS4 (page=0x04 address=0x23) [reset=00h]
      147. 8.9.147 TF_SLOPE1 (page=0x04 address=0x24) [reset=04h]
      148. 8.9.148 TF_SLOPE2 (page=0x04 address=0x25) [reset=08h]
      149. 8.9.149 TF_SLOPE3 (page=0x04 address=0x26) [reset=89h]
      150. 8.9.150 TF_SLOPE4 (page=0x04 address=0x27) [reset=00h]
      151. 8.9.151 TF_TEMP_TH1 (page=0x04 address=0x28) [reset=39h]
      152. 8.9.152 TF_TEMP_TH2 (page=0x04 address=0x29) [reset=80h]
      153. 8.9.153 TF_TEMP_TH3 (page=0x04 address=0x2A) [reset=00h]
      154. 8.9.154 TF_TEMP_TH4 (page=0x04 address=0x2B) [reset=00h]
      155. 8.9.155 TF_MAX_ATTN1 (page=0x04 address=0x2C) [reset=2Dh]
      156. 8.9.156 TF_MAX_ATTN2 (page=0x04 address=0x2D) [reset=6Ah]
      157. 8.9.157 TF_MAX_ATTN3 (page=0x04 address=0x2E) [reset=86h]
      158. 8.9.158 TF_MAX_ATTN4 (page=0x04 address=0x2F) [reset=00h]
      159. 8.9.159 LD_CFG0 (page=0x04 address=0x40) [reset=03h]
      160. 8.9.160 LD_CFG1 (page=0x04 address=0x41) [reset=20h]
      161. 8.9.161 LD_CFG2 (page=0x04 address=0x42) [reset=00h]
      162. 8.9.162 LD_CFG3 (page=0x04 address=0x43) [reset=00h]
      163. 8.9.163 LD_CFG4 (page=0x04 address=0x44) [reset=00h]
      164. 8.9.164 LD_CFG5 (page=0x04 address=0x45) [reset=20h]
      165. 8.9.165 LD_CFG6 (page=0x04 address=0x46) [reset=00h]
      166. 8.9.166 LD_CFG7 (page=0x04 address=0x47) [reset=00h]
      167. 8.9.167 CLD_EFF_1 (page=0x04 address=0x48) [reset=6Ch]
      168. 8.9.168 CLD_EFF_2 (page=0x04 address=0x49) [reset=CCh]
      169. 8.9.169 CLD_EFF_3 (page=0x04 address=0x4A) [reset=CDh]
      170. 8.9.170 CLD_EFF_4 (page=0x04 address=0x4B) [reset=00h]
      171. 8.9.171 LDG_RES1 (page=0x04 address=0x4C) [reset=00h]
      172. 8.9.172 LDG_RES2 (page=0x04 address=0x4D) [reset=00h]
      173. 8.9.173 LDG_RES3 (page=0x04 address=0x4E) [reset=00h]
      174. 8.9.174 LDG_RES4 (page=0x04 address=0x4F) [reset=00h]
      175. 8.9.175 INIT_3 (page=0xFD address=0x3E) [reset=45h]
    10. 8.10 SDOUT Equations
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
    3. 9.3 Design Requirements
    4. 9.4 Detailed Design Procedure
      1. 9.4.1 Mono/Stereo Configuration
      2. 9.4.2 EMI Passive Devices
    5. 9.5 Application Curves
  10. 10Initialization Set Up
    1. 10.1 Initial Device Configuration - Power Up and Software Reset
    2. 10.2 Initial Device Configuration - PWR_MODE0
    3. 10.3 Initial Device Configuration - PWR_MODE1
    4. 10.4 Initial Device Configuration - PWR_MODE2
    5. 10.5 Initial Device Configuration - PWR_MODE3
    6. 10.6 Device Configuration - 44.1 kHz
    7. 10.7 Over Power Protection - OCP Programming
    8. 10.8 DSP Loopback
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Modes
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Community Resources
    3. 13.3 Trademarks
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.9.1 Register Summary Table Page=0x00

AddrRegisterDescriptionSection
0x00PAGEDevice PageSection 8.9.6
0x01SW_RESETSoftware ResetSection 8.9.7
0x02MODE_CTRLDevice operational modeSection 8.9.8
0x03CHNL_0Y Bridge and Channel settingsSection 8.9.9
0x04DC_BLK0SAR Filter and DC Path BlockerSection 8.9.10
0x05DC_BLK1Record DC BlockerSection 8.9.11
0x06MISC_CFG1Misc Configuration 1Section 8.9.12
0x07MISC_CFG2Misc Configuration 2Section 8.9.13
0x08TDM_CFG0TDM Configuration 0Section 8.9.14
0x09TDM_CFG1TDM Configuration 1Section 8.9.15
0x0ATDM_CFG2TDM Configuration 2Section 8.9.16
0x0BLIM_MAX_ATTNLimiterSection 8.9.17
0x0CTDM_CFG3TDM Configuration 3Section 8.9.18
0x0DTDM_CFG4TDM Configuration 4Section 8.9.19
0x0ETDM_CFG5TDM Configuration 5Section 8.9.20
0x0FTDM_CFG6TDM Configuration 6Section 8.9.21
0x10TDM_CFG7TDM Configuration 7Section 8.9.22
0x11TDM_CFG8TDM Configuration 8Section 8.9.23
0x12TDM_CFG9TDM Configuration 9Section 8.9.24
0x13TDM_CFG10TDM Configuration 10Section 8.9.25
0x14TDM_CFG11TDM Configuration 11Section 8.9.26
0x15ICC_CNFG2ICC ModeSection 8.9.27
0x16TDM_CFG12TDM Configuration 12Section 8.9.28
0x17ICLA_CFG0Inter Chip Limiter Alignment 0Section 8.9.29
0x18ICLA_CFG1Inter Chip Gain Alignment 1Section 8.9.30
0x19DG_0Diagnostic SignalSection 8.9.31
0x1ADVCDigital Volume ControlSection 8.9.32
0x1BLIM_CFG0Limiter Configuration 0Section 8.9.33
0x1CLIM_CFG1Limiter Configuration 1Section 8.9.34
0x1DBOP_CFG0Brown Out Prevention 0Section 8.9.35
0x1EBOP_CFG1Brown Out Prevention 1Section 8.9.36
0x1FBOP_CFG2Brown Out Prevention 2Section 8.9.37
0x20BOP_CFG3Brown Out Prevention 3Section 8.9.38
0x21BOP_CFG4Brown Out Prevention 4Section 8.9.39
0x22BOP_CFG5BOP Configuration 5Section 8.9.40
0x23BOP_CFG6Brown Out Prevention 6Section 8.9.41
0x24BOP_CFG7Brown Out Prevention 7Section 8.9.42
0x25BOP_CFG8Brown Out Prevention 8Section 8.9.43
0x26BOP_CFG9Brown Out Prevention 9Section 8.9.44
0x27BOP_CFG10BOP Configuration 10Section 8.9.45
0x28BOP_CFG11Brown Out Prevention 11Section 8.9.46
0x29BOP_CFG12Brown Out Prevention 12Section 8.9.47
0x2ABOP_CFG13Brown Out Prevention 13Section 8.9.48
0x2BBOP_CFG14Brown Out Prevention 14Section 8.9.49
0x2CBOP_CFG15BOP Configuration 15Section 8.9.50
0x2DBOP_CFG17Brown Out Prevention 17Section 8.9.51
0x2EBOP_CFG18Brown Out Prevention 18Section 8.9.52
0x2FBOP_CFG19Brown Out Prevention 19Section 8.9.53
0x30BOP_CFG20Brown Out Prevention 20Section 8.9.54
0x31BOP_CFG21BOP Configuration 21Section 8.9.55
0x32BOP_CFG22Brown Out Prevention 22Section 8.9.56
0x33BOP_CFG23Lowest PVDD MeasuredSection 8.9.57
0x34BOP_CFG24Lowest BOP Attack RateSection 8.9.57
0x35NG_CFG0Noise Gate 0Section 8.9.59
0x36NG_CFG1Noise Gate 1Section 8.9.60
0x37LVS_CFG0Low Voltage SignalingSection 8.9.61
0x38DIN_PDDigital Input Pin Pull DownSection 8.9.62
0x3BINT_MASK0Interrupt Mask 0Section 8.9.63
0x3CINT_MASK1Interrupt Mask 1Section 8.9.64
0x3DINT_MASK4Interrupt Mask 4Section 8.9.65
0x40INT_MASK2Interrupt Mask 2Section 8.9.66
0x41INT_MASK3Interrupt Mask 3Section 8.9.67
0x42INT_LIVE0Live Interrupt Read-back 0Section 8.9.68
0x43INT_LIVE1Live Interrupt Read-back 1Section 8.9.69
0x44INT_LIVE1_0Live Interrupt Read-back 1_0Section 8.9.70
0x47INT_LIVE2Live Interrupt Read-back 2Section 8.9.71
0x48INT_LIVE3Live Interrupt Read-back 3Section 8.9.72
0x49INT_LTCH0Latched Interrupt Read-back 0Section 8.9.73
0x4AINT_LTCH1Latched Interrupt Read-back 1Section 8.9.74
0x4BINT_LTCH1_0Latched Interrupt Read-back 1_0Section 8.9.75
0x4FINT_LTCH2Latched Interrupt Read-back 2Section 8.9.76
0x50INT_LTCH3Latched Interrupt Read-back 3Section 8.9.77
0x51INT_LTCH4Latched Interrupt Read-back 4Section 8.9.78
0x52VBAT_MSBSAR VBAT1S 0Section 8.9.79
0x53VBAT_LSBSAR VBAT1S 1Section 8.9.80
0x54PVDD_MSBSAR PVDD 0Section 8.9.81
0x55PVDD_LSBSAR PVDD 1Section 8.9.82
0x56TEMPSAR ADC Conversion 2Section 8.9.83
0x5CINT_CLK_CFGClock Setting and IRQZSection 8.9.84
0x5DMISC_CFG3Misc Configuration 3Section 8.9.85
0x60CLOCK_CFGClock ConfigurationSection 8.9.86
0x63IDLE_INDIdle channel current optimizationSection 8.9.87
0x64 SAR_SAMP SAR Sampling Time Section 8.9.88
0x65MISC_CFG4Misc Configuration 4Section 8.9.89
0x67TG_CFG0Tone GeneratorSection 8.9.90
0x68CLK_CFGDetect Clock Ration and Sample RateSection 8.9.91
0x6ALV_EN_CFGClass-D and LVS DelaysSection 8.9.92
0x6BNG_CFG2Noise Gate 2Section 8.9.93
0x6CNG_CFG3Noise Gate 3Section 8.9.94
0x6DNG_CFG4Noise Gate 4Section 8.9.95
0x6ENG_CFG5Noise Gate 5Section 8.9.96
0x6FNG_CFG6Noise Gate 6Section 8.9.97
0x70NG_CFG7Noise Gate 7Section 8.9.98
0x71PVDD_UVLOUVLO ThresholdSection 8.9.99
0x73 DMD DAC Modulator Dither Section 8.9.100
0x7EI2C_CKSUMI2C ChecksumSection 8.9.101
0x7FBOOKDevice BookSection 8.9.102