SLASEG6B May 2018 – June 2020 TAS3251
The TAS3251 device supports industry-standard audio data formats, including standard I2S and left-justified. Data formats are selected via Register (P0-R40). All formats require binary two's complement, MSB-first audio data; up to 32-bit audio data is accepted. The data formats are detailed in Figure 24 through Figure 29.
The TAS3251 device also supports right-justified and TDM/DSP data. I2S, LJ, RJ, and TDM/DSP are selected using Register (P0-R40). All formats require binary 2s complement, MSB-first audio data. Up to 32 bits are accepted. Default setting is I2S and 24 bit word length. The I2S slave timing is shown in Figure 3.
shows a detailed timing diagram for the serial audio interface.
In addition to acting as a I2S slave, the TAS3251 device can act as an I2S master, by generating SCLK and LRCK/FS as outputs from the MCLK input. Table 9 lists the registers used to place the device into Master or Slave mode. Please refer to theSerial Audio Port Timing – Master Mode section for serial audio Interface timing requirements in Master Mode. For Slave Mode timing, please refer to to the Serial Audio Port Timing – Slave Mode section.
|P0-R9-B0, B4, and B5||I2S Master mode select|
|P0-R32-D[6:0]||SCLK divider and LRCK/FS divider|