SLASEG6B May 2018 – June 2020 TAS3251
When a clock error is detected on the incoming data clock, the TAS3251 device switches to an internal oscillator and continues to the drive the DAC, while attenuating the data from the last known value. Once this process is complete, the DAC outputs will be hard muted to the ground and the Class-D PWM output will stop switching. The clock error can be monitored at B0-P0-R94 and R95. The clock error status bits are non-latching, except for MCLK halted B0-P0-R95-D which is cleared when read.