SLASEG6B May 2018 – June 2020 TAS3251
|LEGEND: R/W = Read/Write; R = Read only; -n = value after reset|
|4||LTSH||R||Latched Clock Halt – This bit indicates whether MCLK halt has occurred. The bit is cleared when read.
0: MCLK halt has not occurred
|2||CKMF||R||Clock Missing – This bit indicates whether the LRCLK and SCLK are missing (tied low).
0: LRCLK and/or SCLK is present
|1||CSRF||R||Clock Resync Request – This bit indicates whether the clock resynchronization is in progress.
0: Not resynchronizing
|0||CERF||R||Clock Error – This bit indicates whether a clock error has occurred. The bit is cleared when read
0: Clock error has not occurred