SLASEG6B May 2018 – June 2020 TAS3251
The serial audio interface port is a 3-wire serial port with the signals LRCK/FS (pin 25), SCLK (pin 23), and SDIN (pin 24). SCLK is the serial audio bit clock, used to clock the serial data present on SDIN into the serial shift register of the audio interface. Serial data is clocked into the TAS3251 device on the rising edge of SCLK.The LRCK/FS pin is the serial audio left/right word clock or frame sync when the device is operated in TDM Mode.
|FORMAT||DATA BITS||MAXIMUM LRCK/FS FREQUENCY (kHz)||MCLK RATE (fS)||SCLK RATE (fS)|
|I2S/LJ/RJ||32, 24, 20, 16||Up to 96||128 to 3072 (≤ 50 MHz)||64, 48, 32|
|TDM/DSP||32, 24, 20, 16||Up to 48||128 to 3072||125, 256|
|96||128 to 512||125, 256|
The TAS3251 device requires the synchronization of LRCK/FS and system clock, but does not require a specific phase relation between LRCK/FS and system clock.
If the relationship between LRCK/FS and system clock changes more than ±5 MCLK, internal operation is initialized within one sample period and analog outputs are forced to the bipolar zero level until re-synchronization between LRCK/FS and system clock is completed.
If the relationship between LRCK/FS and SCLK are invalid more than 4 LRCK/FS periods, internal operation is initialized within one sample period and analog outputs are forced to the bipolar zero level until re-synchronization between LRCK/FS and SCLK is completed.