6 Specifications

6.1 Absolute Maximum Ratings(1)

MIN MAX UNIT
Supply voltage, DVDD1 and DVDD2 –0.3 3.9 V
Supply voltage, AVDD and AVDD_PWM –0.3 3.9 V
Input voltage 3.3-V digital input –0.5 DVDD + 0.5 V
5-V tolerant(2) digital input –0.5 6
IIK Input clamp current (VI < 0 or VI > 1.8 V ±20 μA
IOK Output clamp current (VO < 0 or VO > 1.8 V) ±20 μA
TSTG Storage temperature range –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) 5-V tolerant signals are RESET, PDN, MUTE, HP_SEL, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDIN3, SDIN4, SDA, and SCL.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±250 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) ±1000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over 0°C to 85°C
MIN NOM MAX UNIT
Digital supply voltage, DVDD1 and DVDD2 3 3.3 3.6 V
Analog supply voltage, AVDD and AVDD_PWM 3 3.3 3.6 V
VIH High‐level input voltage 3.3 V 2 V
5-V tolerant 2
1.8-V LVCMOS (XTL_IN) 1.26
VIL Low‐level input voltage 3.3 V 0.8 V
5-V tolerant 0.8
1.8-V (XTL_IN) 0.54
TA Operating ambient-air temperature 0 25 85 °C
TJ Operating junction temperature 0 105 °C

6.4 Thermal Information

THERMAL METRIC(1) TAS5558 UNIT
DCA (HTSSOP)
56 PINS
RθJA Junction-to-ambient thermal resistance 26.1 °C/W
RθJCtop Junction-to-case (top) thermal resistance 13.0
RθJB Junction-to-board thermal resistance 8.0
ψJT Junction-to-top characterization parameter 0.4
ψJB Junction-to-board characterization parameter 7.9
RθJCbot Junction-to-case (bottom) thermal resistance 0.4
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

At recommended operating conditions - 25 °C Operating Temp, 3.3V Power Supplies with 48kHz input data unless otherwise specified
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage 3.3-V TTL and 5-V tolerant IOH = –4 mA 2.4 V
1.8-V LVCMOS (XTL_OUT) IOH = –0.55 mA 1.44
VOL Low-level output voltage 3.3-V TTL and 5-V tolerant IOL = 4 mA 0.5 V
1.8-V LVCMOS (XTL_OUT) IOL = 0.75 mA 0.5
IOZ High-impedance output current 3.3-V TTL ±20 μA
IIL Low-level input current 3.3-V TTL VI = VIL ±1 μA
1.8-V LVCMOS (XTL_IN) VI = VIL ±1
5-V tolerant(2) VI = 0 V, DVDD = 3 V ±1
IIH High-level input current 3.3-V TTL VI = VIH ±1 μA
1.8-V LVCMOS (XTL_IN) VI = VIH ±1
5-V tolerant(2) VI = 5.5 V, DVDD = 3 V ±1
IDD Input supply current Digital supply voltage, DVDD Input fS = 48 kHz 220 mA
Power down 9
Analog supply voltage, AVDD Input fS = 48 kHz 8
Power down 8

6.6 Dynamic Performance

At recommended operating conditions at (25°C, 3.3V Power Supplies with 48kHz input data) unless otherwise noted.
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
Dynamic range TAS5558 A-weighted (Test Range: 20Hz to 20kHz. fS = 96 kHz). 105 dB
Total harmonic distortion TAS5558 output (1kHz at -1dBFS) 0.01%
Frequency response 32-kHz to 96-kHz sample rates (Test Range 20Hz - 20kHz) ±0.1 dB
176.4, 192-kHz sample rates (Test Range 20Hz - 20kHz) ±0.2

6.7 SRC Performance

ATTRIBUTE VALUE
SRC Latency 102.53125/FSin + 36.46875/FSout
THD+N at 1kHz
Pass Band Ripple (worst case) ±0.05dB
SRC Channel Gain <1 (slightly lower to compensate for ripple)
Stop Band Attenuation 130dB
Pass Band Edge 0.425 FS-in
Stop Band Edge 0.575 FS-in

6.8 Timing I2C Serial Control Port Operation

Timing Characteristics for I2C Interface Signals over recommended operating conditions (unless otherwise noted)
STANDARD MODE FAST MODE UNIT
MIN MAX MIN MAX
fSCL SCL clock frequency 0 100 0 400 kHz
tHD-STA Hold time (repeated) START condition. After this period, the first clock pulse is generated. 4 0.6 μs
tLOW LOW period of the SCL clock 4.7 1.3 μs
tHIGH HIGH period of the SCL clock 4 0.6 μs
tSU-STA Setup time for repeated START 4.7 0.6 μs
tSU-DAT Data setup time 250 200 ns
tHD-DAT Data hold time 0 3.45 0 0.9 μs
tr Rise time of both SDA and SCL, see Figure 1 1000 20 + 0.1 Cb 500 ns
tf Fall time of both SDA and SCL, see Figure 1 300 20 + 0.1 Cb 300 ns
tSU-STO Setup time for STOP condition 4 0.6 μs
tBUF Bus free time between a STOP and START condition 4.7 1.3 μs
Cb Capacitive loads for each bus line 400 400 pF
VnL Noise margin at the LOW level for each connected device (including hysteresis) 0.1 × VDD 0.1 × VDD V
VnH Noise margin at the HIGH level for each connected device (including hysteresis) 0.2 × VDD 0.2 × VDD V

6.9 Reset Timing (RESET)

Control signal parameters over recommended operating conditions (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
tr(DMSTATE) Time to Non PWM Switching low 400 ns
tw(RESET) Pulse duration, RESET active, see Figure 3 400 None ns
tr(I2C_ready) Time to enable I2C 5 ms

6.10 Power-Down (PDN) Timing

Control signal parameters over recommended operating conditions (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
tp(DMSTATE) Time to Non PWM Switching low 650 μs
Number of MCLKs preceding the release of PDN, see Figure 4 5
tsu Device startup time 200 µs
Time to audio output 160 mS

6.11 Back-End Error (BKND_ERR)

Control signal parameters over recommended operating conditions (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
tw(ER) Pulse duration, BKND_ERR active, see Figure 5 350 None ns
tp(valid_low) Minimum amount of time that device asserts VALID low. <100 μs
tp(valid_high) I2C programmable to be between <1mS to 1.2 seconds (to avoid glitching with persistent BKND_ERR) –25 25 % of interval

6.12 Mute Timing (MUTE)

Control signal parameters over recommended operating conditions (unless otherwise noted). See Figure 6
PARAMETER MIN TYP MAX UNIT
td(VOL) Volume ramp time Defined by rate setting(1) ms

Note: No I2C commands during the volume ramp up/down.

6.13 Headphone Select (HP_SEL)

Control signal parameters over recommended operating conditions (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
tw(HP_SEL) Pulse duration, HP_SEL active, see Figure 7 165 ms
td(VOL) Soft volume update time Defined by rate setting(1) ms
t(SW) Switchover time 165 ms

6.14 Switching Characteristics - Clock Signals

PLL input parameters and external filter components over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fMCLKI Frequency, MCLK (1/tcyc2) 2 50 MHz
TAS5558: MCLK duty cycle 40% 50% 60%
TAS5558: MCLK minimum high time ≥2-V MCLK = 49.152 MHz, within the min and max duty cycle constraints 5 ns
TAS5558: MCLK minimum low time ≤0.8-V MCLK = 49.152 MHz, within the min and max duty cycle constraints 5 ns
LRCLK allowable drift before LRCLK reset 10 MCLKs
External PLL filter capacitors SMD 0603 X7R 100 nF
External PLL filter capacitors SMD 0603 X7R 10 nF
External PLL filter resistors SMD 0603, metal film, 1% 200 Ω
External VRA_PWM decoupling C14 SMD 0603 X7R 100 nF

6.15 Switching Characteristics - Serial Audio Port

Serial audio port slave mode over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fSCLKIN SCLK input frequency CL = 30 pF 2.048 12.288 MHz
tsu1 Setup time, LRCLK to SCLK rising edge 10 ns
th1 Hold time, LRCLK from SCLK rising edge 10 ns
tsu2 Setup time, SDIN to SCLK rising edge 10 ns
th2 Hold time, SDIN from SCLK rising edge 10 ns
LRCLK frequency 32 48 192 kHz
SCLK rising edges between LRCLK rising edges 64 64 SCLK edges
SDOUT delay with respect to SCLK output (load = 30pF), see Figure 8 20 ns

6.16 Volume Control

Control signal parameters over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
Maximum attenuation before mute Individual volume, master volume, or a combination of both –127 dB
Maximum gain Individual volume, master volume 18 dB
Maximum volume before the onset of clipping 0-dB input, any modulation limit 0 dB
PSVC range PSVC enabled 12, 18, or 24 dB
PSVC rate fS
PSVC modulation Single sided
PSVC quantization 2048 Steps
PSVC PWM modulation limits PSVC range = 24 dB 6%
(120 : 2048)		 95%
(1944 : 2048)		 dB
TAS5558 scl_sdatiming_les238.gifFigure 1. SCL and SDA Timing
TAS5558 startstoptiming_les238.gifFigure 2. START and STOP Conditions Timing
TAS5558 t0029-04_les270.gifFigure 3. Reset Timing
TAS5558 t0030-03.gifFigure 4. Power-Down Timing
TAS5558 t0031-03.gifFigure 5. Error-Recovery Timing
TAS5558 t0032-02.gifFigure 6. Mute Timing
TAS5558 t0033-02.gifFigure 7. HP_SEL Timing
TAS5558 t0026-01.gifFigure 8. Slave Mode Serial Data Interface Timing

6.17 Typical Characteristics

TAS5558 D001_SLES270.gif
Figure 9. Frequency Response at 48 kHz Sampling Rate with -60 dB Input at 1 kHz
TAS5558 D003_SLES270.gif
Figure 11. Frequency Response at 44.1 kHz Sampling Rate with -60 dB Input at 1 kHz
TAS5558 D002_SLES270.gif
Figure 10. Frequency Response at 48 kHz Sampling Rate with 3 dB Input at 1 kHz
TAS5558 D004_SLES270.gif
Figure 12. Frequency Response at 44.1 kHz Sampling Rate with 3 dB Input at 1 kHz