SLOS782C July   2013  – May  2017 TAS5760L

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Digital I/O Pins
    6. 7.6  Master Clock
    7. 7.7  Serial Audio Port
    8. 7.8  Protection Circuitry
    9. 7.9  Speaker Amplifier in All Modes
    10. 7.10 Speaker Amplifier in Stereo Bridge-Tied Load (BTL) Mode
    11. 7.11 Speaker Amplifier in Mono Parallel Bridge-Tied Load (PBTL) Mode
    12. 7.12 I²C Control Port
    13. 7.13 Typical Idle, Mute, Shutdown, Operational Power Consumption
    14. 7.14 Typical Speaker Amplifier Performance Characteristics (Stereo BTL Mode)
    15. 7.15 Typical Performance Characteristics (Mono PBTL Mode)
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power Supplies
      2. 9.3.2 Speaker Amplifier Audio Signal Path
        1. 9.3.2.1 Serial Audio Port (SAP)
          1. 9.3.2.1.1 I²S Timing
          2. 9.3.2.1.2 Left-Justified
          3. 9.3.2.1.3 Right-Justified
        2. 9.3.2.2 DC Blocking Filter
        3. 9.3.2.3 Digital Boost and Volume Control
        4. 9.3.2.4 Digital Clipper
        5. 9.3.2.5 Closed-Loop Class-D Amplifier
      3. 9.3.3 Speaker Amplifier Protection Suite
        1. 9.3.3.1 Speaker Amplifier Fault Notification (SPK_FAULT Pin)
        2. 9.3.3.2 DC Detect Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Hardware Control Mode
        1. 9.4.1.1 Speaker Amplifier Shut Down (SPK_SD Pin)
        2. 9.4.1.2 Serial Audio Port in Hardware Control Mode
        3. 9.4.1.3 Soft Clipper Control (SFT_CLIP Pin)
        4. 9.4.1.4 Speaker Amplifier Switching Frequency Select (FREQ/SDA Pin)
        5. 9.4.1.5 Parallel Bridge Tied Load Mode Select (PBTL/SCL Pin)
        6. 9.4.1.6 Speaker Amplifier Sleep Enable (SPK_SLEEP/ADR Pin)
        7. 9.4.1.7 Speaker Amplifier Gain Select (SPK_GAIN [1:0] Pins)
        8. 9.4.1.8 Considerations for Setting the Speaker Amplifier Gain Structure
          1. 9.4.1.8.1 Recommendations for Setting the Speaker Amplifier Gain Structure in Hardware Control Mode
      2. 9.4.2 Software Control Mode
        1. 9.4.2.1 Speaker Amplifier Shut Down (SPK_SD Pin)
        2. 9.4.2.2 Serial Audio Port Controls
          1. 9.4.2.2.1 Serial Audio Port (SAP) Clocking
        3. 9.4.2.3 Parallel Bridge Tied Load Mode via Software Control
        4. 9.4.2.4 Speaker Amplifier Gain Structure
          1. 9.4.2.4.1 Speaker Amplifier Gain in Software Control Mode
          2. 9.4.2.4.2 Considerations for Setting the Speaker Amplifier Gain Structure
          3. 9.4.2.4.3 Recommendations for Setting the Speaker Amplifier Gain Structure in Software Control Mode
        5. 9.4.2.5 I²C Software Control Port
          1. 9.4.2.5.1 Setting the I²C Device Address
          2. 9.4.2.5.2 General Operation of the I²C Control Port
          3. 9.4.2.5.3 Writing to the I²C Control Port
          4. 9.4.2.5.4 Reading from the I²C Control Port
    5. 9.5 Register Maps
      1. 9.5.1 Control Port Registers - Quick Reference
      2. 9.5.2 Control Port Registers - Detailed Description
        1. 9.5.2.1  Device Identification Register (0x00)
        2. 9.5.2.2  Power Control Register (0x01)
        3. 9.5.2.3  Digital Control Register (0x02)
        4. 9.5.2.4  Volume Control Configuration Register (0x03)
        5. 9.5.2.5  Left Channel Volume Control Register (0x04)
        6. 9.5.2.6  Right Channel Volume Control Register (0x05)
        7. 9.5.2.7  Analog Control Register (0x06)
        8. 9.5.2.8  Reserved Register (0x07)
        9. 9.5.2.9  Fault Configuration and Error Status Register (0x08)
        10. 9.5.2.10 Reserved Controls (9 / 0x09) - (15 / 0x0F)
        11. 9.5.2.11 Digital Clipper Control 2 Register (0x10)
        12. 9.5.2.12 Digital Clipper Control 1 Register (0x11)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Stereo BTL Using Software Control
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Startup Procedures- Software Control Mode
          2. 10.2.1.2.2 Shutdown Procedures- Software Control Mode
          3. 10.2.1.2.3 Component Selection and Hardware Connections
            1. 10.2.1.2.3.1 I²C Pullup Resistors
            2. 10.2.1.2.3.2 Digital I/O Connectivity
          4. 10.2.1.2.4 Recommended Startup and Shutdown Procedures
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Stereo BTL Using Hardware Control
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Startup Procedures- Hardware Control Mode
          2. 10.2.2.2.2 Shutdown Procedures- Hardware Control Mode
          3. 10.2.2.2.3 Digital I/O Connectivity
        3. 10.2.2.3 Application Curve
      3. 10.2.3 Mono PBTL Using Software Control
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
          1. 10.2.3.2.1 Startup Procedures- Software Control Mode
          2. 10.2.3.2.2 Shutdown Procedures- Software Control Mode
          3. 10.2.3.2.3 Component Selection and Hardware Connections
            1. 10.2.3.2.3.1 I²C Pull-Up Resistors
            2. 10.2.3.2.3.2 Digital I/O Connectivity
        3. 10.2.3.3 Application Curve
      4. 10.2.4 Mono PBTL Using Hardware Control
        1. 10.2.4.1 Design Requirements
        2. 10.2.4.2 Detailed Design Procedure
          1. 10.2.4.2.1 Startup Procedures- Hardware Control Mode
          2. 10.2.4.2.2 Shutdown Procedures- Hardware Control Mode
          3. 10.2.4.2.3 Component Selection and Hardware Connections
          4. 10.2.4.2.4 Digital I/O Connectivity
        3. 10.2.4.3 Application Curve
      5. 10.2.5 Stereo BTL Using Software Control, 32-Pin DAP Package Option
        1. 10.2.5.1 Design Requirements
        2. 10.2.5.2 Detailed Design Procedure
          1. 10.2.5.2.1 Startup Procedures- Software Control Mode
          2. 10.2.5.2.2 Shutdown Procedures- Software Control Mode
          3. 10.2.5.2.3 Component Selection and Hardware Connections
            1. 10.2.5.2.3.1 I²C Pullup Resistors
            2. 10.2.5.2.3.2 Digital I/O Connectivity
          4. 10.2.5.2.4 Recommended Startup and Shutdown Procedures
        3. 10.2.5.3 Application Curve
      6. 10.2.6 Stereo BTL Using Hardware Control, 32-Pin DAP Package Option
        1. 10.2.6.1 Design Requirements
        2. 10.2.6.2 Detailed Design Procedure
          1. 10.2.6.2.1 Startup Procedures- Hardware Control Mode
          2. 10.2.6.2.2 Shutdown Procedures- Hardware Control Mode
          3. 10.2.6.2.3 Digital I/O Connectivity
        3. 10.2.6.3 Application Curve
      7. 10.2.7 Mono PBTL Using Software Control, 32-Pin DAP Package Option
        1. 10.2.7.1 Design Requirements
        2. 10.2.7.2 Detailed Design Procedure
          1. 10.2.7.2.1 Startup Procedures- Software Control Mode
          2. 10.2.7.2.2 Shutdown Procedures- Software Control Mode
          3. 10.2.7.2.3 Component Selection and Hardware Connections
            1. 10.2.7.2.3.1 I²C Pull-Up Resistors
            2. 10.2.7.2.3.2 Digital I/O Connectivity
        3. 10.2.7.3 Application Curve
      8. 10.2.8 Mono PBTL Using Hardware Control, 32-Pin DAP Package Option
        1. 10.2.8.1 Design Requirements
        2. 10.2.8.2 Detailed Design Procedure
          1. 10.2.8.2.1 Startup Procedures- Hardware Control Mode
          2. 10.2.8.2.2 Shutdown Procedures- Hardware Control Mode
          3. 10.2.8.2.3 Component Selection and Hardware Connections
          4. 10.2.8.2.4 Digital I/O Connectivity
        3. 10.2.8.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 DVDD Supply
    2. 11.2 PVDD Supply
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 General Guidelines for Audio Amplifiers
      2. 12.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
      3. 12.1.3 Optimizing Thermal Performance
        1. 12.1.3.1 Device, Copper, and Component Layout
        2. 12.1.3.2 Stencil Pattern
          1. 12.1.3.2.1 PCB Footprint and Via Arrangement
            1. 12.1.3.2.1.1 Solder Stencil
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Audio I/O Configuration:
    • Single Stereo I²S Input
    • Stereo Bridge Tied Load (BTL) or Mono Parallel Bridge Tied Load (PBTL) Operation
    • 32, 44.1, 48, 88.2, 96 kHz Sample Rates
  • General Operational Features:
    • Selectable Hardware or Software Control
    • Integrated Digital Output Clipper
    • Programmable I²C Address (1101100[R/W] or 1101101[R/W])
    • Closed-Loop Amplifier Architecture
    • Adjustable Switching Frequency for Speaker Amplifier
  • Robustness Features:
    • Clock Error, DC, and Short-Circuit Protection
    • Overtemperature and Programmable Overcurrent Protection
  • Audio Performance (PVDD = 12 V, RSPK = 8 Ω, SPK_GAIN[1:0] Pins = 01)
    • Idle Channel Noise = 65 µVrms (A-Wtd)
    • THD+N = 0.09% (at 1 W, 1 kHz)
    • SNR = 100 dB A-Wtd (Ref. to THD+N = 1%)

2 Applications

  • LCD/LED TV and Multipurpose Monitors
  • Sound Bars, Docking Stations, PC Audio
  • General-Purpose Audio Equipment

3 Description

The TAS5760L is a stereo I2S input device which includes hardware and software (I²C) control modes, integrated digital clipper, several gain options, and a wide power supply operating range to enable use in a multitude of applications. The TAS5760L operates with a nominal supply voltage from 4.5 to 15 VDC.

An optimal mix of thermal performance and device cost is provided in the 120-mΩ RDS(ON) of the output MOSFETs. Additionally, a thermally enhanced 48-Pin TSSOP provides excellent operation in the elevated ambient temperatures found in modern consumer electronic devices.

The entire TAS5760xx family is pin-to-pin compatible in the 48-Pin TSSOP package. Alternatively, to achieve the smallest possible solutions size for applications where pin-to-pin compatibility and a headphone or line driver are not required, a 32-Pin TSSOP package is offered for the TAS5760M and TAS5760L devices. The I2C register map in all of the TAS5760xx devices are identical, to ensure low development overhead when choosing between devices based upon system-level requirements.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TAS5760L HTSSOP (48) 12.50 mm × 6.10 mm
HTSSOP (32) 11 mm × 6.2 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

Functional Block Diagram

TAS5760L BD_TAS5760x.gif

Output Power vs PVDD

TAS5760L G001_BTL_384_POvsVDD_SLOS781.png

NOTE:

Thermal Limits were determined via the TAS5760xxEVM