SLASEH7H October   2019  – January 2023 TAS5825M

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
      1. 7.7.1 Bridge Tied Load (BTL) Configuration Curves with Hybrid Modulation
      2. 7.7.2 Parallel Bridge Tied Load (PBTL) Configuration With Hybrid Modulation
      3. 7.7.3 Bridge Tied Load (BTL) Configuration Curves with BD Modulation
      4. 7.7.4 Parallel Bridge Tied Load (PBTL) Configuration With BD Modulation
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power Supplies
      2. 9.3.2 Device Clocking
      3. 9.3.3 Serial Audio Port – Clock Rates
      4. 9.3.4 Clock Halt Auto-Recovery
      5. 9.3.5 Sample Rate on the Fly Change
      6. 9.3.6 Serial Audio Port - Data Formats and Bit Depths
      7. 9.3.7 Digital Audio Processing
      8. 9.3.8 Class D Audio Amplifier
        1. 9.3.8.1 Speaker Amplifier Gain Select
        2. 9.3.8.2 Class D Loop Bandwidth and Switching Frequency Setting
    4. 9.4 Device Functional Modes
      1. 9.4.1 Software Control
      2. 9.4.2 Speaker Amplifier Operating Modes
        1. 9.4.2.1 BTL Mode
        2. 9.4.2.2 PBTL Mode
      3. 9.4.3 Low EMI Modes
        1. 9.4.3.1 Spread Spectrum
        2. 9.4.3.2 Channel to Channel Phase Shift
        3. 9.4.3.3 Multi-Devices PWM Phase Synchronization
          1. 9.4.3.3.1 Phase Synchronization With I2S Clock In Startup Phase
          2. 9.4.3.3.2 Phase Synchronization With GPIO
      4. 9.4.4 Thermal Foldback
      5. 9.4.5 Device State Control
      6. 9.4.6 Device Modulation
        1. 9.4.6.1 BD Modulation
        2. 9.4.6.2 1SPW Modulation
        3. 9.4.6.3 Hybrid Modulation
    5. 9.5 Programming and Control
      1. 9.5.1 I2 C Serial Communication Bus
      2. 9.5.2 I2 C Target Address
        1. 9.5.2.1 Random Write
        2. 9.5.2.2 Sequential Write
        3. 9.5.2.3 Random Read
        4. 9.5.2.4 Sequential Read
        5. 9.5.2.5 DSP Memory Book, Page and BQ update
        6. 9.5.2.6 Checksum
          1. 9.5.2.6.1 Cyclic Redundancy Check (CRC) Checksum
          2. 9.5.2.6.2 Exclusive or (XOR) Checksum
      3. 9.5.3 Control via Software
        1. 9.5.3.1 Startup Procedures
        2. 9.5.3.2 Shutdown Procedures
        3. 9.5.3.3 Protection and Monitoring
          1. 9.5.3.3.1 Overcurrent Limit (Cycle-By-Cycle)
          2. 9.5.3.3.2 Overcurrent Shutdown (OCSD)
          3. 9.5.3.3.3 DC Detect
    6. 9.6 Register Maps
      1. 9.6.1 CONTROL PORT Registers
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Inductor Selections
      2. 10.1.2 Bootstrap Capacitors
      3. 10.1.3 Power Supply Decoupling
      4. 10.1.4 Output EMI Filtering
    2. 10.2 Typical Applications
      1. 10.2.1 2.0 (Stereo BTL) System
      2. 10.2.2 Design Requirements
      3. 10.2.3 Detailed Design procedures
        1. 10.2.3.1 Step One: Hardware Integration
        2. 10.2.3.2 Step Two: Hardware Integration
        3. 10.2.3.3 Step Three: Software Integration
      4. 10.2.4 Application Curves
      5. 10.2.5 MONO (PBTL) Systems
      6. 10.2.6 Advanced 2.1 System (Two TAS5825M Devices)
      7. 10.2.7 Application Curves
    3. 10.3 Power Supply Recommendations
      1. 10.3.1 DVDD Supply
      2. 10.3.2 PVDD Supply
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
        1. 10.4.1.1 General Guidelines for Audio Amplifiers
        2. 10.4.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
        3. 10.4.1.3 Optimizing Thermal Performance
          1. 10.4.1.3.1 Device, Copper, and Component Layout
          2. 10.4.1.3.2 Stencil Pattern
            1. 10.4.1.3.2.1 PCB footprint and Via Arrangement
            2. 10.4.1.3.2.2 Solder Stencil
      2. 10.4.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Development Support
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

CONTROL PORT Registers

Table 9-6 lists the memory-mapped registers for the CONTROL PORT. All register offset addresses not listed in Table 9-6 must be considered as reserved locations and the register contents must not be modified.

Table 9-6 CONTROL PORT Registers
OffsetAcronymRegister NameSection
1hRESET_CTRLRegister 1Go
2hDEVICE_CTRL_1Register 2Go
3hDEVICE_CTRL2Register 3Go
FhI2C_PAGE_AUTO_INCRegister 15Go
28hSIG_CH_CTRLRegister 40Go
29hCLOCK_DET_CTRLRegister 41Go
30hSDOUT_SELRegister 48Go
31hI2S_CTRLRegister 49Go
33hSAP_CTRL1Register 51Go
34hSAP_CTRL2Register 52Go
35hSAP_CTRL3Register 53Go
37hFS_MONRegister 55Go
38hBCK (SCLK)_MONRegister 56Go
39hCLKDET_STATUSRegister 57Go
40hDSP_PGM_MODERegister 64Go
46hDSP_CTRLRegister 70Go
4ChDIG_VOLRegister 76Go
4EhDIG_VOL_CTRL1Register 78Go
4FhDIG_VOL_CTRL2Register 79Go
50hAUTO_MUTE_CTRLRegister 80Go
51hAUTO_MUTE_TIMERegister 81Go
53hANA_CTRLRegister 83Go
54hAGAINRegister 84Go
55hSPI_CLKRegister 85Go
56hEEPROM_CTRL0Register 86Go
57hEEPROM_RD_CMDRegister 87Go
58hEEPROM_ADDR_START0Register 88Go
59hEEPROM_ADDR_START1Register 89Go
5AhEEPROM_ADDR_START2Register 90Go
5BhEEPROM_BOOT_STATUSRegister 91Go
5ChBQ_WR_CTRL1Register 92Go
5EhPVDD_ADCRegister 94Go
60hGPIO_CTRLRegister 96Go
61hGPIO0_SELRegister 97Go
62hGPIO1_SELRegister 98Go
63hGPIO2_SELRegister 99Go
64hGPIO_INPUT_SELRegister 100Go
65hGPIO_OUTRegister 101Go
66hGPIO_OUT_INVRegister 102Go
67hDIE_IDRegister 103Go
68hPOWER_STATERegister 104Go
69hAUTOMUTE_STATERegister 105Go
6AhPHASE_CTRLRegister 106Go
6BhSS_CTRL0Register 107Go
6ChSS_CTRL1Register 108Go
6DhSS_CTRL2Register 109Go
6EhSS_CTRL3Register 110Go
6FhSS_CTRL4Register 111Go
70hCHAN_FAULTRegister 112Go
71hGLOBAL_FAULT1Register 113Go
72hGLOBAL_FAULT2Register 114Go
73hWARNINGRegister 115Go
74hPIN_CONTROL1Register 116Go
75hPIN_CONTROL2Register 117Go
76hMISC_CONTROLRegister 118Go
77hCBC_CONTROLRegister 119Go
78hFAULT_CLEARRegister 120Go

Complex bit access types are encoded to fit into small table cells. Table 9-7 shows the codes that are used for access types in this section.

Table 9-7 CONTROL PORT Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

9.6.1.1 RESET_CTRL Register (Offset = 1h) [reset = 0x00]

RESET_CTRL is shown in Figure 9-16 and described in Table 9-8.

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Figure 9-16 RESET_CTRL Register
76543210
RESERVEDRST_MODRESERVEDRST_REG
R/WWRW
Table 9-8 RESET_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR/W000

This bit is reserved

4RST_DIG_COREW0

WRITE CLEAR BIT

Reset DIG_CORE

WRITE CLEAR BIT Reset Full Digital Core. This bit resets the Full Digital Signal Path (Include DSP coefficient RAM and I2C Control Port Registers), Since the DSP is also reset, the coefficient RAM content is also cleared by the DSP.

0: Normal

1: Reset Full Digital Signal Path

3-1RESERVEDR000

This bit is reserved

0RST_REGW0

WRITE CLEAR BIT

Reset Registers

This bit resets the mode registers back to their initial values. Only reset Control Port Registers, The RAM content is not cleared.

0: Normal

1: Reset I2C Control Port Registers

9.6.1.2 DEVICE_CTRL_1 Register (Offset = 2h) [reset = 0x00]

DEVICE_CTRL_1 is shown in Figure 9-17 and described in Table 9-9.

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Figure 9-17 DEVICE_CTRL_1 Register
76543210
RESERVEDFSW_SELRESERVEDDAMP_PBTLDAMP_MOD
R/WR/WR/WR/WR/W
Table 9-9 DEVICE_CTRL_1 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0

This bit is reserved

6-4FSW_SELR/W000SELECT FSW
000:384K
010:480K
011:576K
100:768K
001:Reserved
101:Reserved
110:Reserved
111:Reserved
3RESERVEDR/W0

This bit is reserved

2DAMP_PBTLR/W00: SET DAMP TO BTL MODE
1:SET DAMP TO PBTL MODE
1-0DAMP_MODR/W00

00:BD MODE 01:1SPW MODE 10:HYBRID MODE

9.6.1.3 DEVICE_CTRL2 Register (Offset = 3h) [reset = 00x10]

DEVICE_CTRL2 is shown in Figure 9-18 and described in Table 9-10.

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Figure 9-18 DEVICE_CTRL2 Register
76543210
RESERVEDDIS_DSPMUTE_LEFTRESERVEDCTRL_STATE
R/WR/WR/WR/WR/W
Table 9-10 DEVICE_CTRL2 Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR/W000

This bit is reserved

4DIS_DSPR/W1DSP reset
When the bit is made 0, DSP starts powering up and send out data. This needs to be made 0 only after all the input clocks are settled so that DMA channels do not go out of sync.
0: Normal operation
1: Reset the DSP
3MUTER/W0Mute both Left and Right Channel
This bit issues soft mute request for both left and right channel. The volume is smoothly ramped down/up to avoid pop/click noise.
0: Normal volume
1: Mute
2RESERVEDR/W0

This bit is reserved

1-0CTRL_STATER/W00device state control register
00: Deep Sleep
01: Sleep
10: Hiz,
11: PLAY

9.6.1.4 I2C_PAGE_AUTO_INC Register (Offset = Fh) [reset = 0x00]

I2C_PAGE_AUTO_INC is shown in Figure 9-19 and described in Table 9-11.

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Figure 9-19 I2C_PAGE_AUTO_INC Register
76543210
RESERVEDPAGE_AUTOINC_REGRESERVED
R/WR/WR/W
Table 9-11 I2C_PAGE_AUTO_INC Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0000

This bit is reserved

3PAGE_AUTOINC_REGR/W0Page auto increment disable
Disable page auto increment mode for non -zero books. When end of page is reached, the page goes back to 8th address location of next page when this bit is 0. When this bit is 1 the page goes to the 0th location of current page itself.
0: Enable Page auto increment
1: Disable Page auto increment
2-0RESERVEDR/W000

This bit is reserved

9.6.1.5 SIG_CH_CTRL Register (Offset = 28h) [reset = 0x00]

SIG_CH_CTRL is shown in Figure 9-20 and described in Table 9-12.

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Figure 9-20 SIG_CH_CTRL Register
76543210
SCLK_RATIO_CONFIGUREFSMODERESERVED
R/WR/WR/W
Table 9-12 SIG_CH_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7-4SCLK_RATIO_CONFIGURER/W0000These bits indicate the configured SCLK ratio, the number of SCLK clocks in one audio frame. Device sets this ratio automatically.
4'b0011:32FS
4'b0101:64FS
4'b0111:128FS
4'b1001:256FS
4'b1011:512FS
3FSMODER/W0FS Speed Mode: These bits select the FS operation mode, which must be set according to the current audio sampling rate and is set manually. If the input Fs is 44.1 kHz/88.2 kHz/176.4 kHz.
4 'b0000 Auto detection
4 'b0100 Reserved
4 'b0110 32 KHz
4 'b1000 44.1 KHz
4 'b1001 48 KHz
4'b1010 88.2 KHz
4 'b1011 96 KHz
4 'b1100 176.4 KHz
4 'b1101 192 KHz
Others Reserved
2-0RESERVEDR/W000

This bit is reserved

9.6.1.6 CLOCK_DET_CTRL Register (Offset = 29h) [reset = 0x00]

CLOCK_DET_CTRL is shown in Figure 9-21 and described in Table 9-13.

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Figure 9-21 CLOCK_DET_CTRL Register
76543210
RESERVEDDIS_DET_PLLDIS_DET_SCLK_RANGEDIS_DET_FSDIS_DET_SCLKDIS_DET_MISSRESERVEDRESERVED
R/WR/WR/WR/WR/WR/WR/WR/W
Table 9-13 CLOCK_DET_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0

This bit is reserved

6DIS_DET_PLLR/W0Ignore PLL overate Detection
This bit controls whether to ignore the PLL overrate detection. The PLL must be slow than 150 MHz or an error is reported. When ignored, a PLL overrate error does not cause a clock error.
0: Regard PLL overrate detection
1: Ignore PLL overrate detection
5DIS_DET_SCLK_RANGER/W0Ignore BCK Range Detection
This bit controls whether to ignore the SCLK range detection. The SCLK must be stable between 256 KHz and 50 MHz or an error is reported. When ignored, a SCLK range error does not cause a clock error.
0: Regard BCK Range detection
1: Ignore BCK Range detection
4DIS_DET_FSR/W0Ignore FS Error Detection
This bit controls whether to ignore the FS Error detection. When ignored, FS error does not cause a clock error. But CLKDET_STATUS reports fs error.
0: Regard FS detection
1: Ignore FS detection
3DIS_DET_SCLKR/W0Ignore SCLK Detection
This bit controls whether to ignore the SCLK detection against LRCK. The SCLK must be stable between 32 FS and 512 FS inclusive or an error is reported. When ignored, a SCLK error does not cause a clock error.
0: Regard SCLK detection
1: Ignore SCLK detection
2DIS_DET_MISSR/W0Ignore SCLK Missing Detection
This bit controls whether to ignore the SCLK missing detection. When ignored an SCLK missing does not cause a clock error.
0: Regard SCLK missing detection
1: Ignore SCLK missing detection
1RESERVEDR/W0

This bit is reserved

0RESERVEDR/W0

This bit is reserved

9.6.1.7 SDOUT_SEL Register (Offset = 30h) [reset = 0x00]

SDOUT_SEL is shown in Figure 9-23 and described in Table 9-14.

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Figure 9-22 SDOUT_SEL Register
76543210
RESERVEDRESERVEDSDOUT_SEL
R/WR/WR/W
Table 9-14 SDOUT_SEL Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W0000000

These bits are reserved

0SDOUT_SELR/W0

SDOUT Select. This bit selects what is being output as SDOUT pin.

0: SDOUT is the DSP output (post-processing)

1: SDOUT is the DSP input (pre-processing)

9.6.1.8 I2S_CTRL Register (Offset = 31h) [reset = 0x00]

I2S_CTRL is shown in Figure 9-23 and described in Table 9-15.

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Figure 9-23 I2S_CTRL Register
76543210
RESERVEDSCLK_INVRESERVEDRESERVEDRESERVEDRESERVED
R/WR/WR/WRRR/W
Table 9-15 I2S_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR/W00

This bit is reserved

5SCLK_INVR/W0SCLK Polarity
This bit sets the inverted SCLK mode. In inverted SCLK mode, the DAC assumes that the LRCK and DIN edges are aligned to the rising edge of the SCLK. Normally the edges are assumed to be aligned to the falling edge of the SCLK
0: Normal SCLK mode
1: Inverted SCLK mode
4RESERVEDR/W0

This bit is reserved

3RESERVEDR0

This bit is reserved

2-1RESERVEDR00

These bits are reserved

0RESERVEDR/W0

This bit is reserved

9.6.1.9 SAP_CTRL1 Register (Offset = 33h) [reset = 0x02]

SAP_CTRL1 is shown in Figure 9-24 and described in Table 9-16.

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Figure 9-24 SAP_CTRL1 Register
76543210
I2S_SHIFT_MSBRESERVEDDATA_FORMATI2S_LRCLK_PULSEWORD_LENGTH
R/WR/WR/WR/WR/W
Table 9-16 SAP_CTRL1 Register Field Descriptions
BitFieldTypeResetDescription
7I2S_SHIFT_MSBR/W0

I2S Shift MSB

6RESERVEDR/W0

This bit is reserved

5-4DATA_FORMATR/W00I2S Data Format
These bits control both input and output audio interface formats for DAC operation.
00: I2S
01: TDM/DSP
10: RTJ
11: LTJ
3-2I2S_LRCLK_PULSER/W00

01: LRCLK pulse < 8 SCLK

1-0WORD_LENGTHR/W10I2S Word Length
These bits control both input and output audio interface sample word lengths for DAC operation.
00: 16 bits
01: 20 bits
10: 24 bits
11: 32 bits

9.6.1.10 SAP_CTRL2 Register (Offset = 34h) [reset = 0x00]

SAP_CTRL2 is shown in Figure 9-25 and described in Table 9-17.

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Figure 9-25 SAP_CTRL2 Register
76543210
I2S_SHIFT
R/W
Table 9-17 SAP_CTRL2 Register Field Descriptions
BitFieldTypeResetDescription
7-0I2S_SHIFTR/W00000000I2S Shift LSB
These bits control the offset of audio data in the audio frame for both input and output. The offset is defined as the number of SCLK from the starting (MSB) of audio frame to the starting of the desired audio sample. MSB [8] locates in Section 9.6.1.9
000000000: offset = 0 SCLK (no offset)
000000001: offset = 1 SCLK
000000010: offset = 2 SCLKs
and
111111111: offset = 512 SCLKs

9.6.1.11 SAP_CTRL3 Register (Offset = 35h) [reset = 0x11]

SAP_CTRL3 is shown in Figure 9-26 and described in Table 9-18.

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Figure 9-26 SAP_CTRL3 Register
76543210
RESERVEDLEFT_DAC_DPATHRESERVEDRIGHT_DAC_DPATH
R/WR/WR/WR/W
Table 9-18 SAP_CTRL3 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR/W00These bits are reserved
5-4LEFT_DAC_DPATHR/W01Left DAC Data Path. These bits control the left channel audio data path connection.

00: Zero data (mute)

01: Left channel data

10: Right channel data

11: Reserved (do not set)

3-2RESERVEDR/W00These bits are reserved
1-0RIGHT_DAC_DPATHR/W01Right DAC Data Path. These bits control the right channel audio data path connection.

00: Zero data (mute)

01: Right channel data

10: Left channel data

11: Reserved (do not set)

9.6.1.12 FS_MON Register (Offset = 37h) [reset = 0x00]

FS_MON is shown in Figure 9-27 and described in Table 9-19.

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Figure 9-27 FS_MON Register
76543210
RESERVEDSCLK_RATIO_HIGHFS
R/WRR
Table 9-19 FS_MON Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR/W00

This bit is reserved

5-4SCLK_RATIO_HIGHR00

2 msbs of detected SCLK ratio

3-0FSR0000These bits indicate the currently detected audio sampling rate.
4 'b0000 FS Error
4 'b0100 16 KHz
4 'b0110 32 KHz
4 'b1000 Reserved
4 'b1001 48 KHz
4 'b1011 96 KHz
4 'b1101 192 KHz
Others Reserved

9.6.1.13 BCK (SCLK)_MON Register (Offset = 38h) [reset = 0x00]

BCK_MON is shown in Figure 9-28 and described in Table 9-20.

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Figure 9-28 BCK (SCLK)_MON Register
76543210
BCLK (SCLK)_RATIO_LOW
R
Table 9-20 BCK_MON Register Field Descriptions
BitFieldTypeResetDescription
7-0BCLK (SCLK)_RATIO_LOWR00000000

These bits indicate the currently detected BCK (SCLK) ratio, the number of BCK (SCLK) clocks in one audio frame.

BCK (SCLK) = 32 FS - 512 FS

9.6.1.14 CLKDET_STATUS Register (Offset = 39h) [reset = 0x00]

CLKDET_STATUS is shown in Figure 9-29 and described in Table 9-21.

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Figure 9-29 CLKDET_STATUS Register
76543210
RESERVEDDET_STATUS
R/WR
Table 9-21 CLKDET_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR/W00

This bit is reserved

5-0DET_STATUSR000000bit0: In auto detection mode(reg_fsmode=0),this bit indicated whether the audio sampling rate is valid or not. In non auto detection mode(reg_fsmode!=0), Fs error indicates that configured fs is different with detected fs. Even FS Error Detection Ignore is set, this flag is also asserted.
bit1: This bit indicates whether the SCLK is valid or not. The SCLK ratio must be stable and in the range of 32-512FS to be valid.
bit2: This bit indicates whether the SCLK is missing or not.
bit3:This bit indicates whether the PLL is locked or not. The PLL is reported as unlocked when the PLL is disabled.
bits4:This bit indicates whether the PLL is overrate
bits5:This bit indicates whether the SCLK is overrate or underrate

9.6.1.15 DSP_PGM_MODE Register (Offset = 40h) [reset = 0x01]

DSP_PGM_MODE is shown in Figure 9-30 and described in Table 9-22.

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Figure 9-30 DSP_PGM_MODE Register
76543210
RESERVEDMODE_SEL
R/WR/W
Table 9-22 DSP_PGM_MODE Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR/W000

This bit is reserved

2-0MODE_SELR/W00001DSP Program Selection
These bits select the DSP program to use for audio processing.
00000 => ram mode
00001 => rom mode 1
00010 => rom mode 2
00011 => rom mode 3

9.6.1.16 DSP_CTRL Register (Offset = 46h) [reset = 0x01]

DSP_CTRL is shown in Figure 9-31 and described in Table 9-23.

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Figure 9-31 DSP_CTRL Register
76543210
RESERVEDUSER_DEFINED_PROCESSING_RATERESERVEDBOOT_FROM_IRAMUSE_DEFAULT_COEFFS
R/WR/WRR/WR/W
Table 9-23 DSP_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR/W000

This bit is reserved

4-3USER_DEFINED_PROCESSING_RATER/W0000:input
01:48k
10:96k
11:192k
2RESERVEDR0This bit is reserved
1RESERVEDR0This bit is reserved
0USE_DEFAULT_COEFFSR/W1Use default coefficients from ZROM this bit controls whether to use default coefficients from ZROM or use the non-default coefficients downloaded to device by the Host
0 : don't use default coefficients from ZROM
1 : use default coefficients from ZROM

9.6.1.17 DIG_VOL Register (Offset = 4Ch) [reset = 30h]

DIG_VOL is shown in Figure 9-32 and described in Table 9-24.

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Figure 9-32 DIG_VOL Register
76543210
PGA_LEFT
R/W
Table 9-24 DIG_VOL Register Field Descriptions
BitFieldTypeResetDescription
7-0PGAR/W00110000Digital Volume
These bits control both left and right channel digital volume. The digital volume is 24 dB to -103 dB in -0.5 dB step.
00000000: +24.0 dB
00000001: +23.5 dB
........
and 00101111: +0.5 dB
00110000: 0.0 dB
00110001: -0.5 dB
.......
11111110: -103 dB
11111111: Mute

9.6.1.18 DIG_VOL_CTRL1 Register (Offset = 4Eh) [reset = 0x33]

DIG_VOL_CTRL1 is shown in Figure 9-33 and described in Table 9-25.

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Figure 9-33 DIG_VOL_CTRL1 Register
76543210
PGA_RAMP_DOWN_SPEEDPGA_RAMP_DOWN_STEPPGA_RAMP_UP_SPEEDPGA_RAMP_UP_STEP
R/WR/WR/WR/W
Table 9-25 DIG_VOL_CTRL1 Register Field Descriptions
BitFieldTypeResetDescription
7-6PGA_RAMP_DOWN_SPEEDR/W00Digital Volume Normal Ramp Down Frequency
These bits control the frequency of the digital volume updates when the volume is ramping down.
00: Update every 1 FS period
01: Update every 2 FS periods
10: Update every 4 FS periods
11: Directly set the volume to zero (Instant mute)
5-4PGA_RAMP_DOWN_STEPR/W11Digital Volume Normal Ramp Down Step
These bits control the step of the digital volume updates when the volume is ramping down.
00: Decrement by 4 dB for each update
01: Decrement by 2 dB for each update
10: Decrement by 1 dB for each update
11: Decrement by 0.5 dB for each update
3-2PGA_RAMP_UP_SPEEDR/W00Digital Volume Normal Ramp Up Frequency
These bits control the frequency of the digital volume updates when the volume is ramping up.
00: Update every 1 FS period
01: Update every 2 FS periods
10: Update every 4 FS periods
11: Directly restore the volume (Instant unmute)
1-0PGA_RAMP_UP_STEPR/W11Digital Volume Normal Ramp Up Step
These bits control the step of the digital volume updates when the volume is ramping up.
00: Increment by 4 dB for each update
01: Increment by 2 dB for each update
10: Increment by 1 dB for each update
11: Increment by 0.5 dB for each update

9.6.1.19 DIG_VOL_CTRL2 Register (Offset = 4Fh) [reset = 0x30]

DIG_VOL_CTRL2 is shown in Figure 9-34 and described in Table 9-26.

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Figure 9-34 DIG_VOL_CTRL2 Register
76543210
FAST_RAMP_DOWN_SPEEDFAST_RAMP_DOWN_STEPRESERVED
R/WR/WR/W
Table 9-26 DIG_VOL_CTRL2 Register Field Descriptions
BitFieldTypeResetDescription
7-6FAST_RAMP_DOWN_SPEEDR/W00Digital Volume Emergency Ramp Down Frequency
These bits control the frequency of the digital volume updates when the volume is ramping down due to clock error or power outage, which usually needs faster ramp down compared to normal soft mute.
00: Update every 1 FS period
01: Update every 2 FS periods
10: Update every 4 FS periods
11: Directly set the volume to zero (Instant mute)
5-4FAST_RAMP_DOWN_STEPR/W11Digital Volume Emergency Ramp Down Step
These bits control the step of the digital volume updates when the volume is ramping down due to clock error or power outage, which usually needs faster ramp down compared to normal soft mute.
00: Decrement by 4 dB for each update
01: Decrement by 2 dB for each update
10: Decrement by 1 dB for each update
11: Decrement by 0.5 dB for each update
3-0RESERVEDR/W0000

This bit is reserved

9.6.1.20 AUTO_MUTE_CTRL Register (Offset = 50h) [reset = 0x07]

AUTO_MUTE_CTRL is shown in Figure 9-35 and described in Table 9-27.

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Figure 9-35 AUTO_MUTE_CTRL Register
76543210
RESERVEDREG_AUTO_MUTE_CTRL
R/WR/W
Table 9-27 AUTO_MUTE_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7-3RESERVEDR/W00000

This bit is reserved

2-0REG_AUTO_MUTE_CTRLR/W111bit0:
0: Disable left channel auto mute
1: Enable left channel auto mute
bit1:
0: Disable right channel auto mute
1: Enable right channel auto mute
bit2: 0:
Auto mute left channel and right channel independently.
1: Auto mute left and right channels only when both channels are about to be auto muted.

9.6.1.21 AUTO_MUTE_TIME Register (Offset = 51h) [reset = 0x00]

AUTO_MUTE_TIME is shown in Figure 9-36 and described in Table 9-28.

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Figure 9-36 AUTO_MUTE_TIME Register
76543210
RESERVEDAUTOMUTE_TIME_LEFTRESERVEDAUTOMUTE_TIME_RIGHT
R/WR/WR/WR/W
Table 9-28 AUTO_MUTE_TIME Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0

This bit is reserved

6-4AUTOMUTE_TIME_LEFTR/W000Auto Mute Time for Left Channel
These bits specify the length of consecutive zero samples at left channel before the channel can be auto muted. The times shown are for 96 kHz sampling rate and scale with other rates.
000: 11.5 ms
001: 53 ms
010: 106.5 ms
011: 266.5 ms
100: 0.535 sec
101: 1.065 sec
110: 2.665 sec
111: 5.33 sec
3RESERVEDR/W0

This bit is reserved

2-0AUTOMUTE_TIME_RIGHTR/W000Auto Mute Time for Right Channel
These bits specify the length of consecutive zero samples at right channel before the channel can be auto muted. The times shown are for 96 kHz sampling rate and scale with other rates.
000: 11.5 ms
001: 53 ms
010: 106.5 ms
011: 266.5 ms
100: 0.535 sec
101: 1.065 sec
110: 2.665 sec
111: 5.33 sec

9.6.1.22 ANA_CTRL Register (Offset = 53h) [reset = 0h]

ANA_CTRL is shown in Figure 9-37 and described in Table 9-29

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Figure 9-37 ANA_CTRL Register
76543210
AMUTE_DLY
R/W
Table 9-29 ANA_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0This bit is reserved
6-5Class D bandwidth controlR/W00

00: 100 kHz

01: 80 kHz

10: 120 kHz

11:175 kHz

With Fsw = 384 kHz, 100 kHz bandwidth is selected for high audio performance. With Fsw = 768 kHz, 175 kHz bandwidth is selected for high audio performance.

4-1RESERVEDR/W0000These bits are reserved
0L and R PWM output phase controlR/W0

0: out of phase

1: in phase

9.6.1.23 AGAIN Register (Offset = 54h) [reset = 0x00]

AGAIN is shown in Figure 9-38 and described in Table 9-30.

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Figure 9-38 AGAIN Register
76543210
RESERVEDANA_GAIN
R/WR/W
Table 9-30 AGAIN Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR/W000

This bit is reserved

4-0ANA_GAINR/W00000Analog Gain Control
This bit controls the analog gain.
00000: 0 dB (29.5V peak voltage)
00001:-0.5db 11111: -15.5 dB

9.6.1.24 SPI_CLK Register (Offset = 55h) [reset = 0x00]

SPI_CLK is shown in Figure 9-39 and described in Table 9-31.

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Figure 9-39 SPI_CLK Register
76543210
RESERVEDSPI_CLK_SEL
R/WR/W
Table 9-31 SPI_CLK Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0000

This bit is reserved

3-0SPI_CLK_SELR/W000000:1.25M
01:2.5M
10:5M
11:10M

9.6.1.25 EEPROM_CTRL0 Register (Offset = 56h) [reset = 0x00]

EEPROM_CTRL0 is shown in Figure 9-40 and described in Table 9-32.

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Figure 9-40 EEPROM_CTRL0 Register
76543210
RESERVEDEEPROM_ADDR_24BITS_ENABLESPI_CLK_RATESPI_INV_POLARSPI_MST_LSBLOAD_EEPROM_START
R/WR/WR/WR/WR/WR/W
Table 9-32 EEPROM_CTRL0 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR/W00

This bit is reserved

5EEPROM_ADDR_24BITS_ENABLER/W0

enable 24 bits mode for EEPROM address

4-3SPI_CLK_RATER/W000: spi clock rate = 1.25 MHz
1: spi clock rate = 2.5 MHz
2: spi clock rate = 5 MHz
3: spi clock rate = 10 MHz
2SPI_INV_POLARR/W00: spi serial data change at post edge SCK
1: spi serial data change at neg edge SCK
1SPI_MST_LSBR/W0

0: msb first 1: lsb first

0LOAD_EEPROM_STARTR/W00: dsp coefficients read from host
1: dsp coefficients read from EEPROM

9.6.1.26 EEPROM_RD_CMD Register (Offset = 57h) [reset = 0x03]

EEPROM_RD_CMD is shown in Figure 9-41 and described in Table 9-33.

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Figure 9-41 EEPROM_RD_CMD Register
76543210
EEPROM_RD_CMD
R/W-00000011
Table 9-33 EEPROM_RD_CMD Register Field Descriptions
BitFieldTypeResetDescription
7-0EEPROM_RD_CMDR/W00000011

EEPROM read command

9.6.1.27 EEPROM_ADDR_START0 Register (Offset = 58h) [reset = 0x00]

EEPROM_ADDR_START0 is shown in Figure 9-42 and described in Table 9-34.

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Figure 9-42 EEPROM_ADDR_START0 Register
76543210
EEPROM_ADDR_START_HIGH
R/W
Table 9-34 EEPROM_ADDR_START0 Register Field Descriptions
BitFieldTypeResetDescription
7-0EEPROM_ADDR_START_HIGHR/W00000000

8 msb of EEPROM read starting address for coefficient

9.6.1.28 EEPROM_ADDR_START1 Register (Offset = 59h) [reset = 0x00]

EEPROM_ADDR_START1 is shown in Figure 9-43 and described in Table 9-35.

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Figure 9-43 EEPROM_ADDR_START1 Register
76543210
EEPROM_ADDR_START_MIDDLE
R/W
Table 9-35 EEPROM_ADDR_START1 Register Field Descriptions
BitFieldTypeResetDescription
7-0EEPROM_ADDR_START_MIDDLER/W00000000

8 middle of EEPROM read starting address for coefficients

9.6.1.29 EEPROM_ADDR_START2 Register (Offset = 5Ah) [reset = 0h]

EEPROM_ADDR_START2 is shown in Figure 9-44 and described in Table 9-36.

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Figure 9-44 EEPROM_ADDR_START2 Register
76543210
EEPROM_ADDR_START_LOW
R/W
Table 9-36 EEPROM_ADDR_START2 Register Field Descriptions
BitFieldTypeResetDescription
7-0EEPROM_ADDR_START_LOWR/W00000000

8 lsb of EEPROM read starting address for coefficients

9.6.1.30 EEPROM_BOOT_STATUS Register (Offset = 5Bh) [reset = 0x00]

EEPROM_BOOT_STATUS is shown in Figure 9-45 and described in Table 9-37.

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Figure 9-45 EEPROM_BOOT_STATUS Register
76543210
RESERVEDLOAD_EEPROM_CRC_ERRORLOAD_EEPROM_DONE
RRR
Table 9-37 EEPROM_BOOT_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR000000

This bit is reserved

1LOAD_EEPROM_CRC_ERRORR00: CRC pass for EEPROM boot load
1: CRC don't pass for EEPROM boot load.
0LOAD_EEPROM_DONER0

Indicate that the EEPROM boot load has been finished.

9.6.1.31 BQ_WR_CTRL1 Register (Offset = 5Ch) [reset = 0x000]

BQ_WR_CTRL1 is shown in Figure 9-46 and described in Table 9-38.

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Figure 9-46 BQ_WR_CTRL1 Register
76543210
RESERVEDBQ_WR_FIRST_COEF
R/WR/W
Table 9-38 BQ_WR_CTRL1 Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W0000000

This bit is reserved

0BQ_WR_FIRST_COEFR/W0

Indicate the first coefficient of a BQ is starting to write.

9.6.1.32 PVDD_ADC Register (Offset = 5Eh) [reset = 0h]

PVDD_ADC is shown in Figure 9-47 and described in Table 9-39.

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Figure 9-47 PVDD_ADC Register
76543210
ADC_DATA_OUT
R
Table 9-39 PVDD_ADC Register Field Descriptions
BitFieldTypeResetDescription
7-0PVDD_ADC[7:0]R00000000

PVDD Voltage = PVDD_ADC[7:0] / 8.428 (V)

223: 26.45V

222: 26.34V

221:26.22V

...

39: 4.63V

38: 4.51V

37: 4.39V

9.6.1.33 GPIO_CTRL Register (Offset = 60h) [reset = 0x00]

GPIO_CTRL is shown in Figure 9-48 and described in Table 9-40.

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Figure 9-48 GPIO_CTRL Register
76543210
RESERVEDGPIO2_OEGPIO1_OEGPIO0_OE
R/WR/WR/WR/W
Table 9-40 GPIO_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7-3RESERVEDR/W0000

This bit is reserved

2GPIO2_OER/W0GPIO2 Output Enable. This bit sets the direction of the GPIO2 pin
0: GPIO2 is input
1: GPIO2 is output
1GPIO1_OER/W0GPIO1 Output Enable This bit sets the direction of the GPIO1 pin
0: GPIO1 is input
1: GPIO1 is output
0GPIO0_OER/W0GPIO0 Output Enable This bit sets the direction of the GPIO0 pin
0: GPIO0 is input
1: GPIO0 is output

9.6.1.34 GPIO0_SEL Register (Offset = 61h) [reset = 0x00]

GPIO0_SEL is shown in Figure 9-49 and described in Table 9-41.

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Figure 9-49 GPIO0_SEL Register
76543210
RESERVEDGPIO0_SEL
R/WR/W
Table 9-41 GPIO0_SEL Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0000

This bit is reserved

3-0GPIO0_SELR/W00000000: off (low)
0001: Reserved
0010: GPIO output value programmed by User in Section 9.6.1.38
0011: Auto mute flag (asserted when both L and R channels are auto muted)
0100: Auto mute flag for left channel
0101: Auto mute flag for right channel
0110: Clock invalid flag (clock error or clock missing)
0111: Reserved
1000: GPIO0 as WARNZ output
1001: Serial audio interface data output (SDOUT)
1011: GPIO0 as FAULTZ output
1100: GPIO0 as SPI CLK
1101: GPIO0 as SPI_PICO
1110: Reserved
1111: Reserved

9.6.1.35 GPIO1_SEL Register (Offset = 62h) [reset = 0x00]

GPIO1_SEL is shown in Figure 9-50 and described in Table 9-42.

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Figure 9-50 GPIO1_SEL Register
76543210
RESERVEDGPIO1_SEL
R/WR/W
Table 9-42 GPIO1_SEL Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0000

This bit is reserved

3-0GPIO1_SELR/W00000000: off (low)
0001: Reserved
0010: GPIO output value programmed by User in Section 9.6.1.38
0011: Auto mute flag (asserted when both L and R channels are auto muted)
0100: Auto mute flag for left channel
0101: Auto mute flag for right channel
0110: Clock invalid flag (clock error or clock missing)
0111: Reserved
1000: GPIO1 as WARNZ output
1001: Serial audio interface data output (SDOUT)
1011: GPIO1 as FAULTZ output
1100: GPIO1 as SPI CLK
1101: GPIO1 as SPI_PICO
1110: Reserved
1111: Reserved

9.6.1.36 GPIO2_SEL Register (Offset = 63h) [reset = 0x00]

GPIO2_SEL is shown in Figure 9-51 and described in Table 9-43.

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Figure 9-51 GPIO2_SEL Register
76543210
RESERVEDGPIO2_SEL
R/WR/W
Table 9-43 GPIO2_SEL Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0000

This bit is reserved

3-0GPIO2_SELR/W00000000: off (low)
0001: Reserved
0010: GPIO output value programmed by User in Section 9.6.1.38
0011: Auto mute flag (asserted when both L and R channels are auto muted)
0100: Auto mute flag for left channel
0101: Auto mute flag for right channel
0110: Clock invalid flag (clock error or clock missing)
0111: Reserved
1000: GPIO2 as WARNZ output
1001: Serial audio interface data output (SDOUT)
1011: GPIO2 as FAULTZ output
1100: GPIO2 as SPI CLK
1101: GPIO2 as SPI_PICO
1110: Reserved
1111: Reserved

9.6.1.37 GPIO_INPUT_SEL Register (Offset = 64h) [reset = 0x00]

GPIO_INPUT_SEL is shown in Figure 9-52 and described in Table 9-44.

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Figure 9-52 GPIO_INPUT_SEL Register
76543210
GPIO_SPI_POCI_SELGPIO_PHASE_SYNC_SELGPIO_RESETZ_SELGPIO_MUTEZ_SEL
R/WR/WR/WR/W
Table 9-44 GPIO_INPUT_SEL Register Field Descriptions
BitFieldTypeResetDescription
7-6GPIO_SPI_POCI_SELR/W0000: N/A
01: GPIO0
10: GPIO1
11: GPIO2
5-4GPIO_PHASE_SYNC_SELR/W0000: N/A
01: GPIO0
10: GPIO1
11: GPIO2
3-2GPIO_RESETZ_SELR/W0000: N/A
01: GPIO0
10: GPIO1
11: GPIO2 cannot be reset by GPIO reset
1-0GPIO_MUTEZ_SELR/W0000: N/A
01: GPIO0
10: GPIO1
11: GPIO2

MUTEZ pin active-low, output driver sets to HiZ state, the output stop switching of the Class D amplifier.

9.6.1.38 GPIO_OUT Register (Offset = 65h) [reset = 0x00]

GPIO_OUT is shown in Figure 9-53 and described in Table 9-45.

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Figure 9-53 GPIO_OUT Register
76543210
RESERVEDGPIO_OUT
R/WR/W
Table 9-45 GPIO_OUT Register Field Descriptions
BitFieldTypeResetDescription
7-3RESERVEDR/W00000

This bit is reserved

2-0GPIO_OUTR/W000bit0: GPIO0 output
bit1: GPIO1 output
bit2: GPIO2 output

9.6.1.39 GPIO_OUT_INV Register (Offset = 66h) [reset = 0x00]

GPIO_OUT_INV is shown in Figure 9-54 and described in Table 9-46.

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Figure 9-54 GPIO_OUT_INV Register
76543210
RESERVEDGPIO_OUT
R/WR/W
Table 9-46 GPIO_OUT_INV Register Field Descriptions
BitFieldTypeResetDescription
7-3RESERVEDR/W00000

This bit is reserved

2-0GPIO_OUTR/W000bit0: GPIO0 output invert
bit1: GPIO1 output invert
bit2: GPIO2 output invert

9.6.1.40 DIE_ID Register (Offset = 67h) [reset = 95h]

DIE_ID is shown in Figure 9-55 and described in Table 9-47.

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Figure 9-55 DIE_ID Register
76543210
DIE_ID
R
Table 9-47 DIE_ID Register Field Descriptions
BitFieldTypeResetDescription
7-0DIE_IDR10010101

DIE ID

9.6.1.41 POWER_STATE Register (Offset = 68h) [reset = 0x00]

POWER_STATE is shown in Figure 9-56 and described in Table 9-48.

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Figure 9-56 POWER_STATE Register
76543210
STATE_RPT
R
Table 9-48 POWER_STATE Register Field Descriptions
BitFieldTypeResetDescription
7-0STATE_RPTR00000000

0: Deep sleep

1: Seep

2: HIZ

3: Play

Others: reserved

9.6.1.42 AUTOMUTE_STATE Register (Offset = 69h) [reset = 0x00]

AUTOMUTE_STATE is shown in Figure 9-57 and described in Table 9-49.

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Figure 9-57 AUTOMUTE_STATE Register
76543210
RESERVEDZERO_RIGHT_MONZERO_LEFT_MON
RRR
Table 9-49 AUTOMUTE_STATE Register Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR000000

This bit is reserved

1ZERO_RIGHT_MONR0

This bit indicates the auto mute status for right channel.

0: Not auto muted

1: Auto muted

0ZERO_LEFT_MONR0

This bit indicates the auto mute status for left channel.

0: Not auto muted

1: Auto muted

9.6.1.43 PHASE_CTRL Register (Offset = 6Ah) [reset = 0]

PHASE_CTRL is shown in Figure 9-58 and described in Table 9-50.

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Figure 9-58 PHASE_CTRL Register
76543210
RESERVEDRAMP_PHASE_SELPHASE_SYNC_SELPHASE_SYNC_EN
R/WR/WR/WR/W
Table 9-50 PHASE_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0000

This bit is reserved

3-2RAMP_PHASE_SELR/W00Select ramp clock phase when multi devices integrated in one system to reduce EMI and peak supply peak current. TI recommends set all devices the same RAMP frequency and same spread spectrum and must be set before driving device into PLAY mode if this feature is needed.
2'b00: phase 0
2'b01: phase 1
2'b10: phase 2
2'b11: phase 3 all of above have a 45 degree of phase shift
1PHASE_SYNC_SELR/W0ramp phase sync sel,
0: is GPIO sync;
1: internal sync
0PHASE_SYNC_ENR/W0

ramp phase sync enable

9.6.1.44 RAMP_SS_CTRL0 Register (Offset = 6Bh) [reset = 0x00]

RAMP_SS_CTRL0 is shown in Figure 9-59 and described in Table 9-51.

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Figure 9-59 SS_CTRL0 Register
76543210
RESERVEDRESERVEDSS_PRE_DIV_SELSS_MANUAL_MODERESERVEDSS_RDM_ENSS_TRI_EN
R/WR/WR/WR/WR/WR/WR/W
Table 9-51 RAMP_SS_CTRL0 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0

This bit is reserved

6RESERVEDR/W0

This bit is reserved

5SS_PRE_DIV_SELR/W0

Select pll clock divide 2 as source clock in manual mode

4SS_MANUAL_MODER/W0

Set ramp ss controller to manual mode

3-2RESERVEDR/W00

This bit is reserved

1SS_RDM_ENR/W0

Random SS enable

0SS_TRI_ENR/W0

Triangle SS enable

9.6.1.45 SS_CTRL1 Register (Offset = 6Ch) [reset = 0x00]

SS_CTRL1 is shown in Figure 9-60 and described in Table 9-52.

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Figure 9-60 SS_CTRL1 Register
76543210
RESERVEDSS_RDM_CTRLSS_TRI_CTRL
R/WR/WR/W
Table 9-52 SS_CTRL1 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0

This bit is reserved

6-4SS_RDM_CTRLR/W000

Add Dither

3-0SS_TRI_CTRLR/W0000

Triangle SS frequency and range control

9.6.1.46 SS_CTRL2 Register (Offset = 6Dh) [reset = 0xA0]

SS_CTRL2 is shown in Figure 9-61 and described in Table 9-53.

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Figure 9-61 SS_CTRL2 Register
76543210
TM_FREQ_CTRL
R/W
Table 9-53 SS_CTRL2 Register Field Descriptions
BitFieldTypeResetDescription
7-0TM_FREQ_CTRLR/W10100000

Control ramp frequency in manual mode, F=61440000/N

9.6.1.47 SS_CTRL3 Register (Offset = 6Eh) [reset = 0x11]

SS_CTRL3 is shown in Figure 9-62 and described in Table 9-54.

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Figure 9-62 SS_CTRL3 Register
76543210
TM_DSTEP_CTRLTM_USTEP_CTRL
R/WR/W
Table 9-54 SS_CTRL3 Register Field Descriptions
BitFieldTypeResetDescription
7-4SS_TM_DSTEP_CTRLR/W0001

Control triangle mode spread spectrum fall step in ramp ss manual mode

3-0SS_TM_USTEP_CTRLR/W0001

Control triangle mode spread spectrum rise step in ramp ss manual mode

9.6.1.48 SS_CTRL4 Register (Offset = 6Fh) [reset = 0x24]

SS_CTRL4 is shown in Figure 9-63 and described in Table 9-55.

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Figure 9-63 SS_CTRL4 Register
76543210
RESERVEDTM_AMP_CTRLSS_TM_PERIOD_BOUNDRY
R/WR/WR/W
Table 9-55 SS_CTRL4 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0

This bit is reserved

6-5TM_AMP_CTRLR/W01

Control ramp amp ctrl in ramp ss manual model

4-0SS_TM_PERIOD_BOUNDRYR/W00100

Control triangle mode spread spectrum boundary in ramp ss manual mode

9.6.1.49 CHAN_FAULT Register (Offset = 70h) [reset = 0x00]

CHAN_FAULT is shown in Figure 9-64 and described in Table 9-56.

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Figure 9-64 CHAN_FAULT Register
76543210
RESERVEDCH1_DC_1CH2_DC_1CH1_OC_ICH2_OC_I
RRRRR
Table 9-56 CHAN_FAULT Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0000

This bit is reserved

3CH1_DC_1R0

Left channel DC fault. Once there is a DC fault, this bit sets to be 1. Class D output sets to Hi-Z. Report by FAULT pin (GPIO). Clear this fault by setting bit 7 of Section 9.6.1.57 to 1 or this bit keeps 1.

2CH2_DC_1R0

Right channel DC fault. Once there is a DC fault, this bit sets to be 1. Class D output sets to Hi-Z. Report by FAULT pin (GPIO). Clear this fault by setting bit 7 of Section 9.6.1.57 to 1 or this bit keeps 1.

1CH1_OC_IR0

Left channel over current fault. Once there is an OC fault, this bit sets to be 1. Class D output sets to Hi-Z. Report by FAULT pin (GPIO). Clear this fault by setting bit 7 of Section 9.6.1.57 to 1 or this bit keeps 1.

0CH2_OC_IR0

Right channel over current fault. Once there is an OC fault, this bit sets to be 1. Class D output sets to Hi-Z. Report by FAULT pin (GPIO). Clear this fault by setting bit 7 of Section 9.6.1.57 to 1 or this bit keeps 1.

9.6.1.50 GLOBAL_FAULT1 Register (Offset = 71h) [reset = 0h]

GLOBAL_FAULT1 is shown in Figure 9-65 and described in Table 9-57.

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Figure 9-65 GLOBAL_FAULT1 Register
76543210
OTP_CRC_ERRORBQ_WR_ERRORLOAD_EEPROM_ERRORRESERVEDRESERVEDCLK_FAULT_IPVDD_OV_IPVDD_UV_I
RRRRRRRR
Table 9-57 GLOBAL_FAULT1 Register Field Descriptions
BitFieldTypeResetDescription
7OTP_CRC_ERRORR0

Indicate OTP CRC check error.

6BQ_WR_ERRORR0

The recent BQ is written failed

5LOAD_EEPROM_ERRORR0

0: EEPROM boot load was done successfully
1: EEPROM boot load was done unsuccessfully

4RESERVEDR0

This bit is reserved

3RESERVEDR0

This bit is reserved

2CLK_FAULT_IR0

Clock fault. Once there is a Clock fault, this bit sets to be 1. Class D output sets to Hi-Z. Report by FAULT pin (GPIO). Clock fault works with an auto-recovery mode, once the clock error removes, device automatically returns to the previous state.

Clear this fault by setting bit 7 of Section 9.6.1.57 to 1 or this bit keeps 1.

1PVDD_OV_IR0

PVDD OV fault. Once there is an OV fault, this bit sets to be 1. Class D output sets to Hi-Z. Report by FAULT pin (GPIO). OV fault works with an auto-recovery mode, once the OV error removes, device automatically returns to the previous state.

Clear this fault by setting bit 7 of Section 9.6.1.57 to 1 or this bit keeps 1.

0PVDD_UV_IR0

PVDD UV fault. Once there is an UV fault, this bit sets to be 1. Class D output sets to Hi-Z. Report by FAULT pin (GPIO). OV fault works with an auto-recovery mode, once the OV error removes, device automatically returns to the previous state.

Clear this fault by setting bit 7 of Section 9.6.1.57 to 1 or this bit keeps 1.

9.6.1.51 GLOBAL_FAULT2 Register (Offset = 72h) [reset = 0h]

GLOBAL_FAULT2 is shown in Figure 9-66 and described in Table 9-58.

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Figure 9-66 GLOBAL_FAULT2 Register
76543210
RESERVEDCBC_FAULT_CH2_ICBC_FAULT_CH1_IOTSD_I
RRRR
Table 9-58 GLOBAL_FAULT2 Register Field Descriptions
BitFieldTypeResetDescription
7-3RESERVEDR0000

This bit is reserved

2CBC_FAULT_CH2_IR0

Right channel cycle by cycle over current fault

1CBC_FAULT_CH1_IR0

Left channel cycle by cycle over current fault

0OTSD_IR0

Over temperature shut down fault.

Once there is a OT fault, this bit sets to be 1. Class D output sets to Hi-Z. Report by FAULT pin (GPIO). OV fault works with an auto-recovery mode, once the OV error removes, device automatically returns to the previous state.

Clear this fault by setting bit 7 of Section 9.6.1.57 to 1 or this bit keeps 1.

9.6.1.52 WARNING Register (Offset = 73h) [reset = 0x00]

WARNING is shown in Figure 9-67 and described in Table 9-59.

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Figure 9-67 WARNING Register
76543210
RESERVEDCBCW_CH1_ICBCW_CH2_IOTW_LEVEL4_IOTW_LEVEL3_IOTW_LEVEL2_IOTW_LEVEL1_I
RRRRRRR
Table 9-59 WARNING Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0

This bit is reserved

5CBCW_CH1_IR0

Left channel cycle by cycle over current warning

4CBCW_CH2_IR0

Right channel cycle by cycle over current warning

3OTW_LEVEL4_IR0

Over temperature warning leve4, 146C

2OTW_LEVEL3_IR0

Over temperature warning leve3, 134C

1OTW_LEVEL2_IR0

Over temperature warning leve2, 122C

0OTW_LEVEL1_IR0

Over temperature warning leve1, 112C

9.6.1.53 PIN_CONTROL1 Register (Offset = 74h) [reset = 0x00]

PIN_CONTROL1 is shown in Figure 9-68 and described in Table 9-60.

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Figure 9-68 PIN_CONTROL1 Register
76543210
MASK_OTSDMASK_DVDD_UVMASK_DVDD_OVMASK_CLK_FAULTRESERVEDMASK_PVDD_UVMASK_DCMASK_OC
R/WR/WR/WR/WRR/WR/WR/W
Table 9-60 PIN_CONTROL1 Register Field Descriptions
BitFieldTypeResetDescription
7MASK_OTSDR/W0

Mask OTSD fault report

6MASK_DVDD_UVR/W0

Mask DVDD UV fault report

5MASK_DVDD_OVR/W0

Mask DVDD OV fault report

4MASK_CLK_FAULTR/W0

Mask clock fault report

3RESERVEDR0

This bit is reserved

2MASK_PVDD_UVR/W0

Mask PVDD UV fault report mask PVDD OV fault report

1MASK_DCR/W0

Mask DC fault report

0MASK_OCR/W0

Mask OC fault report

9.6.1.54 PIN_CONTROL2 Register (Offset = 75h) [reset = 0xF8]

PIN_CONTROL2 is shown in Figure 9-69 and described in Table 9-61.

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Figure 9-69 PIN_CONTROL2 Register
76543210
CBC_FAULT_LATCH_ENCBC_WARN_LATCH_ENCLKFLT_LATCH_ENOTSD_LATCH_ENOTW_LATCH_ENMASK_OTWMASK_CBCWMASK_CBC_FAULT
R/WR/WR/WR/WR/WR/WR/WR/W
Table 9-61 PIN_CONTROL2 Register Field Descriptions
BitFieldTypeResetDescription
7CBC_FAULT_LATCH_ENR/W1

Enable CBC fault latch by setting this bit to 1

6CBC_WARN_LATCH_ENR/W1

Enable CBC warning latch by setting this bit to 1

5CLKFLT_LATCH_ENR/W1

Enable clock fault latch by setting this bit to 1

4OTSD_LATCH_ENR/W1

Enable OTSD fault latch by setting this bit to 1

3OTW_LATCH_ENR/W1

Enable OT warning latch by setting this bit to 1

2MASK_OTWR/W0

Mask OT warning report by setting this bit to 1

1MASK_CBCWR/W0

Mask CBC warning report by setting this bit to 1

0MASK_CBC_FAULTR/W0

Mask CBC fault report by setting this bit to 1

9.6.1.55 MISC_CONTROL Register (Offset = 76h) [reset = 0x00]

MISC_CONTROL is shown in Figure 9-70 and described in Table 9-62.

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Figure 9-70 MISC_CONTROL Register
76543210
DET_STATUS_LATCHRESERVEDOTSD_AUTO_REC_ENRESERVED
R/WR/WR/WR/W
Table 9-62 MISC_CONTROL Register Field Descriptions
BitFieldTypeResetDescription
7DET_STATUS_LATCHR/W0

1:Latch clock detection status

0:Don't latch clock detection status

6-5RESERVEDR/W00

These bits are reserved

4OTSD_AUTO_REC_ENR/W0

OTSD auto recovery enable

3-0RESERVEDR/W0000

This bit is reserved

9.6.1.56 CBC_CONTROL Register (Offset = 77h) [reset = 0x00]

CBC_CONTROL is shown in Figure 9-71 and described in Table 9-63.

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Figure 9-71 CBC_CONTROL Register
76543210
RESERVEDCBC_ENCBC_WARN_ENCBC_FAULT_EN
R/WR/WR/WR/W
Table 9-63 CBC_CONTROL Register Field Descriptions
BitFieldTypeResetDescription
7-3RESERVEDR/W00000

These bits are reserved

2CBC_ENR/W0

Enable CBC function

1CBC_WARN_ENR/W0

Enable CBC warning

0CBC_FAULT_ENR/W0

Enable CBC fault

9.6.1.57 FAULT_CLEAR Register (Offset = 78h) [reset = 0x00]

FAULT_CLEAR is shown in Figure 9-72 and described in Table 9-64.

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Figure 9-72 FAULT_CLEAR Register
76543210
ANALOG_FAULT_CLEARRESERVED
WR/W
Table 9-64 FAULT_CLEAR Register Field Descriptions
BitFieldTypeResetDescription
7ANALOG_FAULT_CLEARW0

WRITE CLEAR BIT once write this bit to 1, device clears analog fault

6-0RESERVEDR/W0000000

This bit is reserved