SLASFD8 May   2025 TAS5830

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
      1. 5.7.1 Bridge Tied Load (BTL) Configuration Curves with BD Modulation
      2. 5.7.2 Bridge Tied Load (BTL) Configuration Curves with 1SPW Modulation
      3. 5.7.3 Parallel Bridge Tied Load (PBTL) Configuration With BD Modulation
      4. 5.7.4 Parallel Bridge Tied Load (PBTL) Configuration With 1SPW Modulation
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Supplies
      2. 6.3.2 Device Clocking
      3. 6.3.3 Serial Audio Port – Clock Rates
      4. 6.3.4 Clock Halt Auto-recovery
      5. 6.3.5 Sample Rate on the Fly Change
      6. 6.3.6 Serial Audio Port - Data Formats and Bit Depths
    4. 6.4 Device Functional Modes
      1. 6.4.1 Software Control
      2. 6.4.2 Speaker Amplifier Operating Modes
        1. 6.4.2.1 BTL Mode
        2. 6.4.2.2 PBTL Mode
      3. 6.4.3 Low EMI Modes
        1. 6.4.3.1 Spread Spectrum
        2. 6.4.3.2 Channel to Channel Phase Shift
        3. 6.4.3.3 Multi-Devices PWM Phase Synchronization
          1. 6.4.3.3.1 Phase Synchronization With I2S Clock In Startup Phase
          2. 6.4.3.3.2 Phase Synchronization With GPIO
      4. 6.4.4 Thermal Foldback
      5. 6.4.5 Device State Control
      6. 6.4.6 Device Modulation
        1. 6.4.6.1 BD Modulation
        2. 6.4.6.2 1SPW Modulation
        3. 6.4.6.3 Hybrid Modulation
      7. 6.4.7 Programming and Control
        1. 6.4.7.1 I2C Serial Communication Bus
        2. 6.4.7.2 Hardware Control Mode
        3. 6.4.7.3 I2C Target Address
          1. 6.4.7.3.1 Random Write
          2. 6.4.7.3.2 Sequential Write
          3. 6.4.7.3.3 Random Read
          4. 6.4.7.3.4 Sequential Read
          5. 6.4.7.3.5 DSP Memory Book, Page and BQ update
          6. 6.4.7.3.6 Checksum
            1. 6.4.7.3.6.1 Cyclic Redundancy Check (CRC) Checksum
            2. 6.4.7.3.6.2 Exclusive or (XOR) Checksum
        4. 6.4.7.4 Control via Software
          1. 6.4.7.4.1 Startup Procedures
          2. 6.4.7.4.2 Shutdown Procedures
        5. 6.4.7.5 Protection and Monitoring
          1. 6.4.7.5.1 Overcurrent Limit (Cycle-By-Cycle)
          2. 6.4.7.5.2 Overcurrent Shutdown (OCSD)
          3. 6.4.7.5.3 DC Detect Error
          4. 6.4.7.5.4 Overtemperature Shutdown (OTSD)
          5. 6.4.7.5.5 PVDD Overvoltage and Undervoltage Error
          6. 6.4.7.5.6 PVDD Drop Detection
          7. 6.4.7.5.7 Clock Fault
  8. 7 Register Maps
    1. 7.1 reg_map Registers
  9. 8 Application and Implementation
    1. 8.1 Typical Applications
      1. 8.1.1 2.0 (Stereo BTL) System
      2. 8.1.2 Mono (PBTL) Systems
    2. 8.2 Power Supply Recommendations
      1. 8.2.1 DVDD Supply
      2. 8.2.2 PVDD Supply
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
        1. 8.3.1.1 General Guidelines for Audio Amplifiers
        2. 8.3.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
        3. 8.3.1.3 Optimizing Thermal Performance
      2. 8.3.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
      2. 9.1.2 Development Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Supports multiple output configurations
    • 2 × 80W, BTL Mode(4Ω, 26V, THD+N=10%)
    • 2 × 65W, BTL Mode(4Ω, 26V, THD+N=1%)
    • 2 × 74W, BTL Mode(6Ω, 30V, THD+N=10%)
    • 2 × 63W, BTL Mode(6Ω, 30V, THD+N=1%)
    • 1 × 151W, PBTL Mode(3Ω, 30V, THD+N=10%)
    • 1 × 131W, PBTL Mode(3Ω, 30V, THD+N=1%)
  • Flexible audio I/O:
    • Supports 32, 44.1, 48, 88.2, 96, 192kHz sample rates
    • I2S, LJ, RJ, 4- 16 channels TDM input
    • SDOUT for audio monitoring, sub-channel, or echo cancellation
    • Supports 3-wire digital audio interface (no MCLK required)
  • High-efficiency Class-D modulation
    • > 90% power efficiency, 70mΩ RDSon
  • Excellent audio performance:
    • THD+N ≤ 0.03% at 1 W, 1kHz, PVDD = 12V
    • SNR ≥ 110dB (A-weighted), ICN ≤ 40µVrms
  • Flexible processing features
    • 3-Band advanced DRC + 2 EQs + AGL + 2 EQs
    • 15 BQs per channel, level meter
    • 96kHz, 192kHz processor sampling
    • Mixer, volume, dynamic EQ, output crossbar
    • PVDD sensing and Class-H algorithm audio signal tracking
    • Rattle suppression, Frequency limiter
  • Flexible power supply configurations
    • PVDD: 4.5V to 30V
    • DVDD and I/O: 1.8V or 3.3V
  • Excellent integrated self-protection:
    • Over-current error (OCE)
    • Cycle-by-cycle current limit supports 4 selectable OC levels
    • Over-temperature warning (OTW)
    • Over-temperature error (OTE)
    • Under and over-voltage lock-out (UVLO/OVLO)
    • PVDD voltage drop detection
  • Easy system integration
    • I2C Software Control (TAS5830 supports both Fast and Fast Plus mode) or Hardware Mode
    • Fewer passives required compared to open-loop devices