SLOSE32A April 2019 – October 2019 TAS6421-Q1
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
OPERATING CURRENT | ||||||
IPVDD_IDLE | PVDD idle current | Channel playing, no audio input | 17 | 23 | mA | |
IVBAT_IDLE | VBAT idle current | Channel playing, no audio input | 28 | 32 | mA | |
IPVDD_STBY | PVDD standby current | STANDBY Active, VDD = 0 V | 0.5 | 1 | µA | |
IVBAT_STBY | VBAT standby current | STANDBY Active, VDD = 0 V | 4 | 6 | µA | |
IVDD | VDD supply current | Channel playing, –60-dB signal | 15 | 18 | mA | |
OUTPUT POWER | ||||||
PO_BTL | Output power per channel, BTL | 4 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C | 20 | 22 | W | |
4 Ω, PVDD = 14.4 V, THD+N = 10%, TC = 75°C | 25 | 27 | ||||
2 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C | 38 | 40 | ||||
2 Ω, PVDD = 14.4 V, THD+N = 10%, TC = 75°C | 42 | 45 | ||||
4 Ω, PVDD = 25 V, THD+N = 1%, TC = 75°C | 50 | 55 | ||||
4 Ω, PVDD = 25 V, THD+N = 10%, TC = 75°C | 70 | 75 | ||||
EFFP | Power efficiency | 1 channel operating at 25-W output power, 4 Ω load, PVDD = 14.4 V, TC = 25°C, including inductor losses | 86% | |||
AUDIO PERFORMANCE | ||||||
Vn | Output noise voltage | Zero input, A-weighting, gain level 1, PVDD = 14.4 V | 42 | µV | ||
Zero input, A-weighting, gain level 2, PVDD = 14.4 V | 55 | |||||
Zero input, A-weighting, gain level 3, PVDD = 18 V | 67 | |||||
Zero input, A-weighting, gain level 4, PVDD = 25 V | 85 | |||||
GAIN | Peak Output Voltage/dBFS | gain level 1, Register 0x01, bit 1-0 = 00 | 7.5 | V/FS | ||
gain level 2, Register 0x01, bit 1-0 = 01 | 15 | |||||
gain level 3, Register 0x01, bit 1-0 = 10 | 21 | |||||
gain level 4, Register 0x01, bit 1-0 = 11 | 29 | |||||
PSRR | Power-supply rejection ratio | PVDD = 14.4 Vdc + 1 VRMS, f = 1 kHz | 75 | dB | ||
THD+N | Total harmonic distortion + noise | 0.02% | ||||
LINE OUTPUT PERFORMANCE | ||||||
Vn_LINEOUT | LINE output noise voltage | Zero input, A-weighting, channel set to LINE MODE | 42 | µV | ||
VO_LINEOUT | LINE output voltage | 0dB input, channel set to LINE MODE | 5.5 | VRMS | ||
THD+N | Line output total harmonic distortion + noise | VO = 2 VRMS, channel set to LINE MODE | 0.01% | |||
DIGITAL INPUT PINS | ||||||
VIH | Input logic level high | 70 | %VDD | |||
VIL | Input logic level low | 30 | %VDD | |||
IIH | Input logic current, high | VI = VDD | 15 | µA | ||
IIL | Input logic current, low | VI = 0 | -15 | µA | ||
PWM OUTPUT STAGE | ||||||
RDS(on) | FET drain-to-source resistance | Not including bond wire and package resistance | 90 | mΩ | ||
OVERVOLTAGE (OV) PROTECTION | ||||||
VPVDD_OV | PVDD overvoltage shutdown | 27.0 | 27.8 | 28.8 | V | |
VPVDD_OV_HYS | PVDD overvoltage shutdown hysteresis | 0.8 | V | |||
VVBAT_OV | VBAT overvoltage shutdown | 20 | 21.5 | 23 | V | |
VVBAT_OV_HYS | VBAT overvoltage shutdown hysteresis | 0.6 | V | |||
UNDERVOLTAGE (UV) PROTECTION | ||||||
VBATUV | VBAT undervoltage shutdown | 4 | 4.5 | V | ||
VBATUV_HYS | VBAT undervoltage shutdown hysteresis | 0.2 | V | |||
PVDDUV | PVDD undervoltage shutdown | 4 | 4.5 | V | ||
PVDDUV_HYS | PVDD undervoltage shutdown hysteresis | 0.2 | V | |||
BYPASS VOLTAGES | ||||||
VGVDD | Gate drive bypass pin voltage | 7 | V | |||
VAVDD | Analog bypass pin voltage | 6 | V | |||
VVCOM | Common bypass pin voltage | 2.5 | V | |||
VVREG | Regulator bypass pin voltage | 5.5 | V | |||
POWER-ON RESET (POR) | ||||||
VPOR | VDD voltage for POR | 2.1 | 2.7 | V | ||
VPOR_HYS | VDD POR recovery hysteresis voltage | 0.5 | V | |||
OVERTEMPERATURE (OT) PROTECTION | ||||||
OTW(i) | Channel overtemperature warning | 150 | °C | |||
OTSD(i) | Channel overtemperature shutdown | 175 | °C | |||
OTW | Global junction overtemperature warning | 130 | °C | |||
OTSD | Global junction overtemperature shutdown | 160 | °C | |||
OTHYS | Overtemperature hysteresis | 15 | °C | |||
LOAD OVERCURRENT PROTECTION | ||||||
ILIM | Overcurrent cycle-by-cycle limit | OC Level 1 | 4.0 | 4.8 | A | |
OC Level 2 | 6.0 | 6.5 | A | |||
ISD | Overcurrent shutdown | OC Level 1, Any short to supply, ground, or other channels | 7 | A | ||
OC Level 2, Any short to supply, ground, or other channels | 9 | A | ||||
MUTE MODE | ||||||
GMUTE | Output attenuation | 100 | dB | |||
CLICK AND POP | ||||||
VCP | Output click and pop voltage | ITU-R 2k filter, High-Z/MUTE to Play, Play to Mute/High-Z | 7 | mV | ||
DC OFFSET | ||||||
VOFFSET | Output offset voltage | 2 | 5 | mV | ||
DC DETECT | ||||||
DCFAULT | Output DC fault protection | 2 | 2.5 | V | ||
DIGITAL OUTPUT PINS | ||||||
VOH | Output voltage for logic level high | I = ±2 mA | 90 | %VDD | ||
VOL | Output voltage for logic level low | I = ±2 mA | 10 | %VDD | ||
tDELAY_CLIPDET | Signal delay when output clipping detected | 20 | µs | |||
LOAD DIAGNOSTICS | ||||||
S2P | Resistance to detect a short from OUT pin(s) to PVDD | 500 | Ω | |||
S2G | Resistance to detect a short from OUT pin(s) to ground | 200 | Ω | |||
SL | Shorted load detection tolerance | ±0.5 | Ω | |||
OL | Open load | 40 | 70 | Ω | ||
TDC_DIAG | DC diagnostic time | 100 | ms | |||
LO | Line output diagnostic detection | 6 | kΩ | |||
TLINE_DIAG | Line output diagnostic time | Not including the preceeding DC_DIAG time | 40 | ms | ||
ACIMP | AC impedance accuracy | Gain linearity, ƒ = 19 kHz, RL = 2 Ω to 16 Ω | 25% | |||
ACIMP | AC impedance accuracy | Offset | ±0.5 | Ω | ||
TAC_DIAG | AC diagnostic time | 170 | ms | |||
I2C_ADDR PINS | ||||||
tI2C_ADDR | Time delay needed for I2C address set-up | 300 | µs | |||
I2C CONTROL PORT | ||||||
tBUS | Bus free time between a STOP and START condition | 1.3 | µs | |||
th1 | Hold time, SCL to SDA | 0 | ns | |||
th2 | Hold time, start condition to SCL | 0.6 | µs | |||
tSTART | I2C startup time after VDD power on reset | 12 | ms | |||
tRISE | Rise time, SCL and SDA | 300 | ns | |||
tFALL | Fall time, SCL and SDA | 300 | ns | |||
tSU1 | Setup, SDA to SCL | 100 | ns | |||
tSU2 | Setup, SCL to start condition | 0.6 | µs | |||
tSU3 | Setup, SCL to stop condition | 0.6 | µs | |||
tW(H) | Required pulse duration SCL High | 0.6 | µs | |||
tW(L) | Required pulse duration SCL Low | 1.3 | µs | |||
SERIAL AUDIO PORT | ||||||
DMCLK, DSCLK | Allowable input clock duty cycle | 45% | 50% | 55% | ||
fMCLK | Supported MCLK frequencies | 128, 256, or 512 | 128 | 512 | xFS | |
fMCLK_Max | Maximum frequency | 25 | MHz | |||
tSCY | SCLK pulse cycle time | 40 | ns | |||
tSCL | SCLK pulse-with LOW | 16 | ns | |||
tSCH | SCLK pulse-with HIGH | 16 | ns | |||
tRISE/FALL | Rise and fall time | <5 | ns | |||
tSF | SCLK rising edge to FSYNC edge | 8 | ns | |||
tFS | FSYNC rising edge to SCLK edge | 8 | ns | |||
tDS | DATA set-up time | 8 | ns | |||
tDH | DATA hold time | 8 | ns | |||
ci | Input capacitance, pins MCLK, SCLK, FSYNC, SDIN1 | 10 | pf | |||
TLA | Latency from input to output measured in FSYNC sample count | FSYNC = 44.1 kHz or 48 kHz | 30 | |||
FSYNC = 96 kHz | 12 |