SLOSE73A June 2021 – November 2021 TAS6424E-Q1
PRODUCTION DATA
The Miscellaneous Control 2 register is shown in Figure 9-16 and described in Table 9-12.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PWM FREQUENCY | RESERVED | SDM_OSR | OUTPUT PHASE | |||
R/W-0 | R/W-110 | R/W-0 | R/W-0 | R/W-10 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R/W | 0 |
RESERVED |
6–4 | PWM FREQUENCY | R/W | 110 |
000: 8 × fS (352.8 kHz / 384 kHz) 001: 10 × fS (441 kHz / 480 kHz) 010: RESERVED 011: RESERVED 100: RESERVED 101: 38 × fS (1.68 MHz / 1.82 MHz) 110: 44 × fS (1.94 MHz / 2.11 MHz) 111: 48 × fS (2.12 MHz / not supported) |
3 | RESERVED | R/W | 0 |
RESERVED |
2 | SDM_OSR | R/W | 0 |
0: 64x OSR 1: 128x OSR |
1–0 | OUTPUT PHASE | R/W | 10 |
The channel-to-channel PWM output phase, PHASE_SEL[2:0], is selected with the two LSB bits in this register and the MSB bit from Miscellaneous Control 5 Register (address = 0x28) [default = 0x0A], Bit 5. WARNING: The MSB in Miscellaneous Control 5 Register, Bit 5 must be set to '1' before the device exits STANDBY. The default value MSB of '0' is not supported by this device. 0xx: RESERVED 010: RESERVED (default, must be changed) 100: RESERVED 101: CH1- 0, CH2- 210, CH3- 60, CH4- 270 110: CH1- 0, CH2- 225, CH3- 90, CH4- 315 111: CH1- 0, CH2- 240, CH3- 120, CH4- 360 |