SLOS948 February 2019 TAS6424M-Q1
In a typical system, the VBAT and PVDD supplies are both connected to the vehicle battery and power up at the same time. The VDD supply is recommended to be applied 200µs before the VBAT and PVDD supplies start ramping to their recommended operating range. As reference, please see Figure 39. If this is unfeasible and VBAT / PVDD will be supplied before VDD, it is recommended wait 200µs after VDD is supplied before pulling the STANDBY pin high. As reference, please see Figure 40.
When removing power from the device, TI recommends to deassert the VBAT and PVDD supplies together first, which provides the lowest click and pop performance, and VDD last. During powering down, VDD must remain available for at least 1.01s after all output stages got set to Hi-Z. To shorten this required delay to 46ms, a 20kOhm parallel resistor between AVDD and AVSS can be added.